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AN6081 - Interfacing 90-nm Cypress Asynchronous SRAMs in Legacy Systems | Cypress Semiconductor

AN6081 - Interfacing 90-nm Cypress Asynchronous SRAMs in Legacy Systems

Last Updated: 
Feb 18, 2018

Click here to download Application Note (PDF File)

AN6081 describes the potential issues faced when using the new-generation 90-nm Cypress SRAMs in applications that rely on legacy 5-V processors. This application note also discusses the troubleshooting methods on output voltage issues when migrating to the new devices. Usage recommendations when you opt to use Cypress SRAMs in such applications are also provided.


Applications have evolved from using 5-V power supply to using 3-V and 1.8-V supply. Cypress’s Asynchronous SRAM devices operate over all of these voltage ranges. This application note discusses a case of incompatibility between output voltage thresholds of 90-nm SRAM devices and input voltage thresholds of processors or controllers that are interfaced with these SRAMs in legacy 5-V systems. A recommendation to use an old generation Cypress SRAM is given to match the requirements in such cases.

Please see the illustrations and the application note below for details.

Processor receiving data from SRAM on a read operation:


SRAM in Output Mode Diagram

Actual V OH SRAM Diagram

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.