You are here

Home › Technical Documents › Application Notes › AN6017 - Differences in Implementation of 65 nm QDR™ II/DDR II and QDR II+/DDR II+ Memory Interfaces

AN6017 - Differences in Implementation of 65 nm QDR™ II/DDR II and QDR II+/DDR II+ Memory Interfaces | Cypress Semiconductor

AN6017 - Differences in Implementation of 65 nm QDR™ II/DDR II and QDR II+/DDR II+ Memory Interfaces

Last Updated: 
Nov 23, 2015
Version: 
*D
This document describes the following:
  • Description of the QDRII+/DDRII+ devices
  • Differences between QDRII/DDRII and QDRII+/DDRII+ functionality and timing
  • Design changes that need to be considered by system designers when migrating from QDRII/DDRII to QDRII+/DDRII+ devices

 

The table below outlines the differences between the QDRII/DDRII and QDRII+/DDRII+ SRAMs

Differences between QDRII / DDRII and QDRII+ / DDRII+

  QDR II / DDRII QDRII+ / DDRII+ Remark
Frequency (PLL enabled)-65nm technology device

120 MHz ~ 333 MHz

 120 MHz ~ 550 MHz Burst of 2 QDRII+/DDRII+ support 333
MHz and Burst of 4 QDRII+/DDRII+
support 550 MHz as highest frequency.
Organization x8, x9, x18, x36 x18, x36 -
VDD 1.8 V ± 0.1 V 1.8 V ± 0.1 V -
VDDQ 1.8 V ± 0.1 V or 1.5 V ± 0.1 V 1.8 V ± 0.1 V or 1.5 V ± 0.1 V -
Read latency 1.5 clocks 2.0 & 2.5 clocks QDRII+/DDRII+ read latency is not user selectable. Offered as two different devices.
Input clocks Single ended (K,K#) Single ended     (K,K#) -
Output clocks (C,C#) Yes No -
ODT (On-Die Termination) No Offered in ODT and Non ODT versions -
A0 (DDR B2) Yes No -
A0, A1 (DDR B4) Yes No -
Echo clock number 1 Pair 1 Pair Echo clocks are single ended
PKG 165 ball FBGA 165 ball FBGA -
Individual byte write (BW0#, BW1#) Yes Yes -

 

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.

Related Files

File Title Language Size Last Updated
AN6017 Differences in Implementation of 65 nm QDR II/DDR II and QDR II+/DDR II+ Memory Interfaces.pdf English 673.6 KB 11/23/2015
AN6017 Differences in Implementation of 65 nm QDR II/DDR II and QDR II+/DDR II+ Memory Interfaces (Chinese).pdf Chinese 668.79 KB 08/25/2015
AN6017 Differences in Implementation of 65 nm QDR II/DDR II and QDR II+/DDR II+ Memory Interfaces (Japanese).pdf Japanese 751.93 KB 08/25/2015

Need help? Ask a question and find answers in the Cypress Developer Community Forums.

Low/intermittent bandwidth users tip: Firefox and Chrome browsers will allow downloads to be resumed if your connection is lost during download.

Related Resources

Application Notes
AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide 05/14/2020
AN42468 - On-Die Termination for QDR(R) II+/DDR II+ SRAMs 05/28/2020
Datasheets
CY7C1526KV18, CY7C1513KV18, CY7C1515KV18: 72-Mbit QDR® II SRAM Four-Word Burst Architecture 11/20/2017
CY7C1518KV18, CY7C1520KV18: 72-Mbit DDR II SRAM Two-Word Burst Architecture 02/13/2018
CY7C1565KV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 11/30/2017
CY7C1525KV18, CY7C1512KV18, CY7C1514KV18: 72-Mbit QDR® II SRAM Two-Word Burst Architecture 01/29/2018
CY7C1568KV18, CY7C1570KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 03/15/2016
CY7C1310JV18, CY7C1910JV18, CY7C1312JV18, CY7C1314JV18: 18-Mbit QDR® II SRAM 2-Word Burst Architecture 05/28/2020
CY7C1548KV18, CY7C1550KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C1543KV18, CY7C1545KV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C15632KV18, 72-Mbit QDR(R) II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C1523KV18: 72-Mbit DDR II SIO SRAM Two-Word Burst Architecture 01/29/2018
CY7C1521KV18, 72-Mbit DDR II SRAM Four-Word Burst Architecture 11/30/2017
CY7C1248KV18, CY7C1250KV18: 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, CY7C1415KV18 : 36-Mbit QDR® II SRAM Four-Word Burst Architecture 11/28/2017
CY7C2263KV18, CY7C2265KV18: 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/06/2016
CY7C2268KV18, CY7C2270KV18: 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/28/2020
CY7C1425KV18, CY7C1412KV18, CY7C1414KV18: 36-Mbit QDR® II SRAM Two-Word Burst Architecture 01/29/2018
CY7C1418KV18, CY7C1420KV18: 36-Mbit DDR II SRAM Two-Word Burst Architecture 01/29/2018
CY7C1268KV18, CY7C1270KV18: 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 11/29/2017
CY7C1423KV18/CY7C1424KV18, 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 01/29/2018
CY7C1243KV18/CY7C1245KV18, 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 02/13/2018
CY7C1263KV18/CY7C1265KV18, 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C1312KV18, CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 11/30/2017
CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, CY7C1315KV18: 18-Mbit QDR® II SRAM Four-Word Burst Architecture 02/13/2018
CY7C1318KV18, CY7C1320KV18: 18-Mbit DDR II SRAM Two-Word Burst Architecture 01/29/2018
CY7C1319KV18, CY7C1321KV18: 18-Mbit DDR II SRAM Four-Word Burst Architecture 01/29/2018
CY7C1392KV18, CY7C1393KV18: 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 01/29/2018
CY7C1163KV18, CY7C1165KV18: 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C1143KV18, CY7C1145KV18: 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 02/03/2016
CY7C2163KV18/CY7C2165KV18, 18-MBIT QDR(R) II+ SRAM FOUR-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) WITH ODT 05/28/2020
CY7C1148KV18, CY7C1150KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C1168KV18, CY7C1170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
CY7C25682KV18, CY7C25702KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 03/15/2016
CY7C25442KV18: 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 11/28/2017
CY7C25632KV18, CY7C25652KV18: 72-Mbit QDR®II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 11/30/2017
CY7C1623KV18: 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture 05/28/2020
CY7C1643KV18/CY7C1645KV18, 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 11/29/2017
CY7C1648KV18, CY7C1650KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C1663KV18/CY7C1665KV18, 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2663KV18, CY7C2665KV18: 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 11/27/2017
CY7C2642KV18, CY7C2644KV18: 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 01/08/2016
CY7C1613KV18/CY7C1615KV18, 144-MBIT QDR® II SRAM FOUR-WORD BURST ARCHITECTURE 01/29/2018
CY7C1618KV18, CY7C1620KV18: 144-Mbit DDR II SRAM Two-Word Burst Architecture 12/03/2017
CY7C2670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
CY7C1625KV18, CY7C1612KV18, CY7C1614KV18: 144-Mbit QDR® II SRAM Two-Word Burst Architecture 02/15/2018
CY7C2563XV18, CY7C2565XV18: 72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 11/27/2017
CY7C1562XV18, CY7C1564XV18: 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C1568XV18, CY7C1570XV18: 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2562XV18, CY7C2564XV18: 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 09/03/2017
CY7C1563XV18, CY7C1565XV18: 72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2568XV18, CY7C2570XV18: 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 08/27/2015
CY7C1262XV18, CY7C1264XV18: 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C1263XV18, CY7C1265XV18: 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C1268XV18, CY7C1270XV18: 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C2262XV18/CY7C2264XV18, 36-Mbit QDR(R) II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/28/2020
CY7C2263XV18, CY7C2265XV18: 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/28/2020
CY7C2268XV18/CY7C2270XV18, 36-MBIT DDR II+ XTREME SRAM TWO-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) WITH ODT 05/28/2020
CY7C1668KV18, CY7C1670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 12/03/2017
CYRS1542AV18, CYRS1544AV18: 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology 05/28/2020
CYRS1543AV18, CYRS1545AV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture with RadStop™ Technology 05/28/2020
CY7C2245KV18: 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 05/30/2020
CY7C25422KV18: 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 01/29/2018

Related Resources

Application Notes (2)
Datasheets (62)

Related Pages

DDR-II CIO
DDR-II SIO
DDR-II+ CIO
QDR-II
QDR-II+
Synchronous SRAMs

Related Parts

CY7C1143KV18-450BZC
CY7C1145KV18-400BZXC
CY7C1145KV18-400BZXCT
CY7C1145KV18-450BZXC
CY7C1148KV18-400BZC
CY7C1148KV18-400BZXC
CY7C1150KV18-400BZXI
CY7C1163KV18-400BZI
CY7C1163KV18-550BZC
CY7C1165KV18-400BZC