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AN54908 - Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates | Cypress Semiconductor

AN54908 - Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates

Last Updated: 
Mar 02, 2021
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This application note describes the accelerated neutron testing procedure and test conditions that are applied during device qualification for Cypress SRAM devices. It covers Synchronous SRAM, Asynchronous SRAM, More Battery Life¿ MoBL®SRAM, and Nonvolatile SRAM (nvSRAM).

This application note describes the accelerated neutron testing procedure and test conditions that are applied during device qualification for Cypress SRAM devices. It covers Synchronous SRAM, Asynchronous SRAM, More Battery Life™ MoBL® SRAM, and Nonvolatile SRAM (nvSRAM) but does not contain soft error rate (SER) data for any of the SRAMs. Individual datasheets for Synchronous SRAMs list the derived accelerated neutron failure rates.

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Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

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Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.

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File Title Language Size Last Updated
AN54908 Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates.pdf English 465.15 KB 03/02/2021
AN54908 Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates (Chinese).pdf Chinese 546.05 KB 08/20/2015
AN54908 Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates (Japanese).pdf Japanese 645.79 KB 08/20/2015

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Related Resources

Datasheets
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CY7C1461AV33, CY7C1463AV33: 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture 06/09/2020
CY7C1351G: 4-Mbit (128 K × 36) Flow-through SRAM with NoBL™ Architecture 06/09/2020
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CY7C1327G: 4-Mbit (256 K × 18) Pipelined Sync SRAM 11/21/2016
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CY7C1338G: 4-Mbit (128 K × 32) Flow-Through Sync SRAM 11/21/2016
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CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
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CY7C1618KV18, CY7C1620KV18: 144-Mbit DDR II SRAM Two-Word Burst Architecture 12/03/2017
CY7C2670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
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CY7C1380DV33/CY7C1382DV33, 18-MBIT (512 K X 36/1 M X 18) PIPELINED SRAM 01/05/2016
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CY7C1371DV33: 18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture 03/11/2016
CY7C1441AV25, CY7C1447AV25: 36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM 03/09/2016
CY7C1463BV33: 36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture 01/11/2016
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CY7C1263XV18, CY7C1265XV18: 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C1268XV18, CY7C1270XV18: 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C2262XV18/CY7C2264XV18, 36-Mbit QDR(R) II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/28/2020
CY7C2263XV18, CY7C2265XV18: 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/28/2020
CY7C2268XV18/CY7C2270XV18, 36-MBIT DDR II+ XTREME SRAM TWO-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) WITH ODT 05/28/2020
CY7C1668KV18, CY7C1670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 12/03/2017
CY7C1384D: 18-Mbit (512 K × 32) Pipelined SRAM 01/08/2016
CY7C1385D, 18-MBIT (512 K X 32) FLOW-THROUGH SRAM 01/05/2016
CY7C1481BV25: 72-Mbit (2 M × 36) Flow-Through SRAM 05/28/2020
CY7C1484BV25: 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM 01/08/2016
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CY7C1325H: 4-Mbit (256 K × 18) Flow-Through Sync SRAM 07/17/2016
CY7C1363D: 9-Mbit (512 K × 18) Flow-Through SRAM 11/04/2020
CY7C2245KV18: 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 05/30/2020
CY7C1354D: 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture 05/30/2020
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