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AN54908 - Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates | Cypress Semiconductor

AN54908 - Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates

Last Updated: 
Jul 20, 2017
Version: 
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This application note describes the accelerated neutron testing procedure and test conditions that are applied during device qualification for Cypress SRAM devices. It covers Synchronous SRAM, Asynchronous SRAM, More Battery Life™ MoBL® SRAM, and Nonvolatile SRAM (nvSRAM) but does not contain soft error rate (SER) data for any of the SRAMs. Individual datasheets for Synchronous SRAMs list the derived accelerated neutron failure rates.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.

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File Title Language Size Last Updated
AN54908 Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates.pdf English 465.15 KB 07/20/2017
AN54908 Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates (Chinese).pdf Chinese 546.05 KB 08/20/2015
AN54908 Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates (Japanese).pdf Japanese 645.79 KB 08/20/2015

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Related Resources

Datasheets
CY7C1328G: 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM 11/20/2016
CY7C1470V33, CY7C1472V33, CY7C1474V33: 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture 04/30/2019
CY7C1471V25: 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture 11/21/2016
CY7C1480V33: 72-Mbit (2M x 36) Pipelined Sync SRAM 09/06/2017
CY7C1471V33: 72-Mbit (2 M × 36) Flow-through SRAM with NoBL™ Architecture 02/15/2018
CY7C1470V25, CY7C1472V25, CY7C1474V25: 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture 01/29/2018
CY7C1441AV33: 36-Mbit (1 M x 36) Flow-Through SRAM 08/21/2015
CY7C1461AV33, CY7C1463AV33: 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture 07/28/2016
CY7C1351G: 4-Mbit (128 K × 36) Flow-through SRAM with NoBL™ Architecture 01/29/2018
CY7C1353G: 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture 04/30/2019
CY7C1327G: 4-Mbit (256 K × 18) Pipelined Sync SRAM 11/21/2016
CY7C1352G: 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture 11/21/2016
CY7C1350G: 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture 05/13/2019
CY7C1345G: 4-Mbit (128 K × 36) Flow-Through Sync SRAM 11/21/2016
CY7C1338G: 4-Mbit (128 K × 32) Flow-Through Sync SRAM 11/21/2016
CY7C1325G: 4-Mbit (256 K × 18) Flow-Through Sync SRAM 11/21/2016
CY7C1360C, CY7C1362C: 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM 04/30/2019
CY7C1366C, CY7C1367C: 9-Mbit (256 K × 36/512 K × 18) Pipelined DCD Sync SRAM 04/30/2019
CY7C1354CV25, CY7C1356CV25: 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL™ Architecture 05/13/2019
CY7C1355C, CY7C1357C: 9-Mbit (256 K × 36 / 512 K × 18) Flow-Through SRAM with NoBL™ Architecture 01/29/2018
CY7C1380D, CY7C1380F, CY7C1382D: 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM 03/30/2016
CY7C1381D, CY7C1383D, CY7C1383F: 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM 06/19/2017
CY7C1302DV25: 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture 11/30/2017
CY7C1329H: 2-Mbit (64K x 32) Pipelined Sync SRAM 01/31/2018
CY7C1354C, CY7C1356C: 9-Mbit (256 K × 36/512 K × 18) Pipelined SRAM with NoBL Architecture 04/09/2018
CY7C1470BV25, CY7C1472BV25: 72-Mbit (2 M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture 02/15/2018
CY7C1470BV33, CY7C1472BV33, CY7C1474BV33: 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture 02/15/2018
CY7C1471BV25: 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL Architecture 05/19/2016
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CY7C1471BV33, CY7C1473BV33: 72-Mbit (2 M × 36/4 M × 18) Flow-Through SRAM with NoBL™ Architecture 01/29/2018
CY7C1361C, CY7C1363C: 9-Mbit (256 K × 36/512 K × 18) Flow-Through SRAM 04/30/2019
CY7C1339G: 4-Mbit (128 K × 32) Pipelined Sync SRAM 11/21/2016
CY7C1347G: 4-Mbit (128 K × 36) Pipelined Sync SRAM 04/22/2019
CY7C1526KV18, CY7C1513KV18, CY7C1515KV18: 72-Mbit QDR® II SRAM Four-Word Burst Architecture 11/20/2017
CY7C1518KV18, CY7C1520KV18: 72-Mbit DDR II SRAM Two-Word Burst Architecture 02/13/2018
CY7C1565KV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 11/30/2017
CY7C1525KV18, CY7C1512KV18, CY7C1514KV18: 72-Mbit QDR® II SRAM Two-Word Burst Architecture 01/29/2018
CY7C1480BV33, CY7C1482BV33: 72-Mbit (2 M × 36/4 M × 18) Pipelined Sync SRAM 03/07/2018
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CY7C1310JV18, CY7C1910JV18, CY7C1312JV18, CY7C1314JV18: 18-Mbit QDR® II SRAM 2-Word Burst Architecture 06/20/2014
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CY7C1543KV18, CY7C1545KV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C15632KV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/30/2018
CY7C1523KV18: 72-Mbit DDR II SIO SRAM Two-Word Burst Architecture 01/29/2018
CY7C1521KV18, 72-Mbit DDR II SRAM Four-Word Burst Architecture 11/30/2017
CY7C1248KV18, CY7C1250KV18: 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
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CY7C2268KV18, CY7C2270KV18: 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
CY7C1425KV18, CY7C1412KV18, CY7C1414KV18: 36-Mbit QDR® II SRAM Two-Word Burst Architecture 01/29/2018
CY7C1418KV18, CY7C1420KV18: 36-Mbit DDR II SRAM Two-Word Burst Architecture 01/29/2018
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CY7C1423KV18/CY7C1424KV18, 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 01/29/2018
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CY7C1263KV18/CY7C1265KV18, 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C1312KV18, CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 11/30/2017
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CY7C1319KV18, CY7C1321KV18: 18-Mbit DDR II SRAM Four-Word Burst Architecture 01/29/2018
CY7C1392KV18, CY7C1393KV18: 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 01/29/2018
CY7C1163KV18, CY7C1165KV18: 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C1143KV18, CY7C1145KV18: 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 02/03/2016
CY7C2163KV18/CY7C2165KV18, 18-MBIT QDR® II+ SRAM FOUR-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) WITH ODT 01/29/2018
CY7C1148KV18, CY7C1150KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C1168KV18, CY7C1170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
CY7C25682KV18, CY7C25702KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 03/15/2016
CY7C25442KV18: 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 11/28/2017
CY7C25632KV18, CY7C25652KV18: 72-Mbit QDR®II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 11/30/2017
CY7C1623KV18: 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture 03/29/2016
CY7C1643KV18/CY7C1645KV18, 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 11/29/2017
CY7C1648KV18, CY7C1650KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C1663KV18/CY7C1665KV18, 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2663KV18, CY7C2665KV18: 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 11/27/2017
CY7C2642KV18, CY7C2644KV18: 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 01/08/2016
CY7C1613KV18/CY7C1615KV18, 144-MBIT QDR® II SRAM FOUR-WORD BURST ARCHITECTURE 01/29/2018
CY7C1618KV18, CY7C1620KV18: 144-Mbit DDR II SRAM Two-Word Burst Architecture 12/03/2017
CY7C2670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
CY7C1625KV18, CY7C1612KV18, CY7C1614KV18: 144-Mbit QDR® II SRAM Two-Word Burst Architecture 02/15/2018
CY7C1481BV33: 72-Mbit (2 M × 36) Flow-Through SRAM 09/13/2018
CY7C1364CV33: 9-Mbit (256 K × 32) Pipelined Sync SRAM 08/25/2015
CY7C1440AV25, CY7C1446AV25: 36-Mbit (1 M × 36/512 K × 72) Pipelined Sync SRAM 01/08/2016
CY7C1380DV33/CY7C1382DV33, 18-MBIT (512 K X 36/1 M X 18) PIPELINED SRAM 01/05/2016
CY7C1460BV25, CY7C1462BV25: 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture 01/06/2016
CY7C1371DV33: 18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture 03/11/2016
CY7C1441AV25, CY7C1447AV25: 36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM 03/09/2016
CY7C1463BV33: 36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture 01/11/2016
CY7C2563XV18, CY7C2565XV18: 72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 11/27/2017
CY7C1562XV18, CY7C1564XV18: 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C1568XV18, CY7C1570XV18: 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2562XV18, CY7C2564XV18: 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 09/03/2017
CY7C1563XV18, CY7C1565XV18: 72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2568XV18, CY7C2570XV18: 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 08/27/2015
CY7C1262XV18, CY7C1264XV18: 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C1263XV18, CY7C1265XV18: 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C1268XV18, CY7C1270XV18: 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2262XV18, CY7C2264XV18: 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 12/10/2017
CY7C2263XV18, CY7C2265XV18: 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
CY7C2268XV18, CY7C2270XV18: 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
CY7C1668KV18, CY7C1670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 12/03/2017
CY7C1384D: 18-Mbit (512 K × 32) Pipelined SRAM 01/08/2016
CY7C1385D, 18-MBIT (512 K X 32) FLOW-THROUGH SRAM 01/05/2016
CY7C1481BV25: 72-Mbit (2 M × 36) Flow-Through SRAM 08/28/2015
CY7C1484BV25: 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM 01/08/2016
CYRS1542AV18, CYRS1544AV18: 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology 07/04/2019
CYRS1543AV18, CYRS1545AV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture with RadStop™ Technology 07/04/2019
CY7C1325H: 4-Mbit (256 K × 18) Flow-Through Sync SRAM 07/17/2016
CY7C1363D: 9-Mbit (512 K × 18) Flow-Through SRAM 07/17/2016
CY7C2245KV18: 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 01/29/2018
CY7C1354D: 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture 02/13/2018
CY7C4122KV13, CY7C4142KV13: 144-Mbit QDR™-IV XP SRAM 05/03/2017
CY7C4121KV13, CY7C4141KV13: 144-Mbit QDR™-IV HP SRAM 08/15/2017
CY7C4022KV13/CY7C4042KV13, 72-Mbit QDR™-IV XP SRAM 08/15/2017
CY7C4021KV13, CY7C4041KV13: 72-Mbit QDR™-IV HP SRAM 08/15/2017
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