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AN54908 - Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates | Cypress Semiconductor

AN54908 - Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates

Last Updated: 
May 28, 2020
Version: 
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This application note describes the accelerated neutron testing procedure and test conditions that are applied during device qualification for Cypress SRAM devices. It covers Synchronous SRAM, Asynchronous SRAM, More Battery Life¿ MoBL®SRAM, and Nonvolatile SRAM (nvSRAM).

This application note describes the accelerated neutron testing procedure and test conditions that are applied during device qualification for Cypress SRAM devices. It covers Synchronous SRAM, Asynchronous SRAM, More Battery Life™ MoBL® SRAM, and Nonvolatile SRAM (nvSRAM) but does not contain soft error rate (SER) data for any of the SRAMs. Individual datasheets for Synchronous SRAMs list the derived accelerated neutron failure rates.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.

Related Files

File Title Language Size Last Updated
AN54908 Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates.pdf English 464.83 KB 05/26/2020
AN54908 Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates (Chinese).pdf Chinese 546.05 KB 08/20/2015
AN54908 Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates (Japanese).pdf Japanese 645.79 KB 08/20/2015

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Datasheets
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CY7C1327G: 4-Mbit (256 K × 18) Pipelined Sync SRAM 11/21/2016
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CY7C1338G: 4-Mbit (128 K × 32) Flow-Through Sync SRAM 11/21/2016
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CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
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CY7C1441AV25, CY7C1447AV25: 36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM 03/09/2016
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CY7C1268XV18, CY7C1270XV18: 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C2262XV18/CY7C2264XV18, 36-Mbit QDR(R) II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/28/2020
CY7C2263XV18, CY7C2265XV18: 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/28/2020
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CY7C1385D, 18-MBIT (512 K X 32) FLOW-THROUGH SRAM 01/05/2016
CY7C1481BV25: 72-Mbit (2 M × 36) Flow-Through SRAM 05/28/2020
CY7C1484BV25: 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM 01/08/2016
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CY7C1325H: 4-Mbit (256 K × 18) Flow-Through Sync SRAM 07/17/2016
CY7C1363D: 9-Mbit (512 K × 18) Flow-Through SRAM 07/17/2016
CY7C2245KV18: 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 05/30/2020
CY7C1354D: 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture 05/30/2020
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CY7C4121KV13, CY7C4141KV13: 144-Mbit QDR™-IV HP SRAM 08/15/2017
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