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AN54908 - Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates | Cypress Semiconductor

AN54908 - Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates

Last Updated: 
Mar 02, 2021
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This application note describes the accelerated neutron testing procedure and test conditions that are applied during device qualification for Cypress SRAM devices. It covers Synchronous SRAM, Asynchronous SRAM, More Battery Life¿ MoBL®SRAM, and Nonvolatile SRAM (nvSRAM).

This application note describes the accelerated neutron testing procedure and test conditions that are applied during device qualification for Cypress SRAM devices. It covers Synchronous SRAM, Asynchronous SRAM, More Battery Life™ MoBL® SRAM, and Nonvolatile SRAM (nvSRAM) but does not contain soft error rate (SER) data for any of the SRAMs. Individual datasheets for Synchronous SRAMs list the derived accelerated neutron failure rates.

Dear valued customer,

Thank you for choosing our products. They come with all the know-how and passion that our engineers have put into it. As you probably already know, Cypress is now Infineon. This is a major step for our company, but also for the good of you. 

Reliability and business continuity are of utmost importance for us. Hence, we remain fully committed to honoring existing customer and distributor relationships. This includes offering the legacy Cypress product portfolio. We thank you very much for your trusting support.

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Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.

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File Title Language Size Last Updated
AN54908 Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates.pdf English 465.15 KB 03/02/2021
AN54908 Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates (Chinese).pdf Chinese 546.05 KB 08/20/2015
AN54908 Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates (Japanese).pdf Japanese 645.79 KB 08/20/2015

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Related Resources

Datasheets
CY7C1328G: 4-Mbit (256 K × 18) Pipelined DCD Sync SRAM 11/20/2016
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CY7C1471V25: 72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture 11/21/2016
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CY7C1470V25, CY7C1472V25, CY7C1474V25: 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined SRAM with NoBL™ Architecture 06/09/2020
CY7C1441AV33: 36-Mbit (1 M x 36) Flow-Through SRAM 06/09/2020
CY7C1461AV33, CY7C1463AV33: 36-Mbit (1 M × 36/2 M × 18) Flow-Through SRAM with NoBL™ Architecture 06/09/2020
CY7C1351G: 4-Mbit (128 K × 36) Flow-through SRAM with NoBL™ Architecture 06/09/2020
CY7C1353G: 4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture 06/09/2020
CY7C1327G: 4-Mbit (256 K × 18) Pipelined Sync SRAM 11/21/2016
CY7C1352G: 4-Mbit (256 K × 18) Pipelined SRAM with NoBL™ Architecture 11/21/2016
CY7C1350G: 4-Mbit (128 K × 36) Pipelined SRAM with NoBL™ Architecture 06/08/2020
CY7C1345G: 4-Mbit (128 K × 36) Flow-Through Sync SRAM 11/21/2016
CY7C1338G: 4-Mbit (128 K × 32) Flow-Through Sync SRAM 11/21/2016
CY7C1325G: 4-Mbit (256 K × 18) Flow-Through Sync SRAM 11/21/2016
CY7C1360C/CY7C1362C, 9-MBIT (256K X 36/512K X 18) PIPELINED SRAM 06/08/2020
CY7C1366C, CY7C1367C: 9-Mbit (256 K × 36/512 K × 18) Pipelined DCD Sync SRAM 06/09/2020
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CY7C1380D, CY7C1380F, CY7C1382D: 18-Mbit (512 K × 36/1 M × 18) Pipelined SRAM 03/30/2016
CY7C1381D, CY7C1383D, CY7C1383F: 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM 06/19/2017
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CY7C1329H: 2-Mbit (64K x 32) Pipelined Sync SRAM 01/31/2018
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CY7C1470BV25, CY7C1472BV25: 72-Mbit (2 M × 36/4 M × 18) Pipelined SRAM with NoBL™ Architecture 02/15/2018
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CY7C1312KV18, CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 11/30/2017
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CY7C1148KV18, CY7C1150KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
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CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
CY7C25682KV18, CY7C25702KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 03/15/2016
CY7C25442KV18: 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 05/30/2021
CY7C25632KV18, CY7C25652KV18: 72-Mbit QDR®II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 11/30/2017
CY7C1623KV18: 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture 05/28/2020
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CY7C1648KV18, CY7C1650KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C1663KV18/CY7C1665KV18, 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2663KV18, CY7C2665KV18: 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/30/2021
CY7C2642KV18, CY7C2644KV18: 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 01/08/2016
CY7C1613KV18/CY7C1615KV18, 144-MBIT QDR® II SRAM FOUR-WORD BURST ARCHITECTURE 01/29/2018
CY7C1618KV18, CY7C1620KV18: 144-Mbit DDR II SRAM Two-Word Burst Architecture 05/30/2021
CY7C2670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
CY7C1625KV18, CY7C1612KV18, CY7C1614KV18: 144-Mbit QDR® II SRAM Two-Word Burst Architecture 01/06/2021
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CY7C1440AV25, CY7C1446AV25: 36-Mbit (1 M × 36/512 K × 72) Pipelined Sync SRAM 01/08/2016
CY7C1380DV33/CY7C1382DV33, 18-MBIT (512 K X 36/1 M X 18) PIPELINED SRAM 01/05/2016
CY7C1460BV25, CY7C1462BV25: 36-Mbit (1 M × 36/2 M × 18) Pipelined SRAM with NoBL™ Architecture 01/06/2016
CY7C1371DV33: 18-Mbit (512 K × 36) Flow-Through SRAM with NoBL™ Architecture 03/11/2016
CY7C1441AV25, CY7C1447AV25: 36-Mbit (1 M × 36/512 K × 72) Flow-Through SRAM 03/09/2016
CY7C1463BV33: 36-Mbit (2 M × 18) Flow-Through SRAM with NoBL™ Architecture 01/11/2016
CY7C2563XV18, CY7C2565XV18: 72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 11/27/2017
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CY7C1568XV18, CY7C1570XV18: 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2562XV18, CY7C2564XV18: 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 09/03/2017
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CY7C2568XV18, CY7C2570XV18: 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 08/27/2015
CY7C1262XV18, CY7C1264XV18: 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C1263XV18, CY7C1265XV18: 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C1268XV18, CY7C1270XV18: 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C2262XV18/CY7C2264XV18, 36-Mbit QDR(R) II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/28/2020
CY7C2263XV18, CY7C2265XV18: 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/28/2020
CY7C2268XV18/CY7C2270XV18, 36-MBIT DDR II+ XTREME SRAM TWO-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) WITH ODT 05/28/2020
CY7C1668KV18, CY7C1670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 12/03/2017
CY7C1384D: 18-Mbit (512 K × 32) Pipelined SRAM 01/08/2016
CY7C1385D, 18-MBIT (512 K X 32) FLOW-THROUGH SRAM 01/05/2016
CY7C1481BV25: 72-Mbit (2 M × 36) Flow-Through SRAM 05/28/2020
CY7C1484BV25: 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM 01/08/2016
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CYRS1543AV18, CYRS1545AV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture with RadStop™ Technology 05/28/2020
CY7C1325H: 4-Mbit (256 K × 18) Flow-Through Sync SRAM 07/17/2016
CY7C1363D: 9-Mbit (512 K × 18) Flow-Through SRAM 11/04/2020
CY7C2245KV18: 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 05/30/2020
CY7C1354D: 9-Mbit (256 K × 36) Pipelined SRAM with NoBL™ Architecture 05/30/2020
CY7C4122KV13, CY7C4142KV13: 144-Mbit QDR™-IV XP SRAM 05/03/2017
CY7C4121KV13, CY7C4141KV13: 144-Mbit QDR™-IV HP SRAM 08/15/2017
CY7C4022KV13/CY7C4042KV13, 72-Mbit QDR™-IV XP SRAM 08/15/2017
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