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AN5073 - Guidelines for Selecting the Reference Clock Input of the HOTLink II™ Device in SMPTE SDI Video Applications | Cypress Semiconductor

AN5073 - Guidelines for Selecting the Reference Clock Input of the HOTLink II™ Device in SMPTE SDI Video Applications

Last Updated: 
Oct 09, 2018
Version: 
*B

The purpose of this application note is to analyze one of the contributors of jitter in the serial output, namely the phase noise present in the reference source. The bit-rate clock that clocks the shift register is a multiple of the reference clock. Hence, a portion of the jitter on the reference clock is transferred to the serial bit rate clock which in turn translates to jitter at the serial data output.



This application note presents the phase noise of five sample clock sources for which the HOTLink II serial data output meets the SMPTE jitter specifications for both alignment and timing jitter.

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