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AN49576 - Interfacing ADMUX SRAM Processors to West Bridge® Antioch | Cypress Semiconductor

AN49576 - Interfacing ADMUX SRAM Processors to West Bridge® Antioch

Last Updated: 
Aug 03, 2017
Version: 
*E

Cypress West Bridge® Antioch™ provides High-Speed USB peripheral and mass storage control capabilities to the host processor through its host Processor-port (P-port). This application note presents a physical interconnect example of interfacing a host processor with an address data multiplexed (ADMUX) SRAM interface to Antioch, using Antioch’s Pseudo-CRAM P-port interface.

Introduction

The rapid growth of the mobile and embedded device market demands new features and capabilities such as High-Speed USB connectivity and support for the latest mass storage devices. However, the system processor cannot keep in pace with the high speed evolution of new technologies and standards. Cypress West Bridge® Antioch™ (CYBW0124AB) device is the solution to this discrepancy. It is designed to enable handset designers easily add new functionalities in their designs.

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