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AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide | Cypress Semiconductor

AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide

Last Updated: 
May 14, 2020
Version: 
*I

Cypress Quad Data Rate™ (QDR®)-II, QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for networking and data storage applications that provide up to 80 GBps data transfer rate. The purpose of this application note is to assist system designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking and termination techniques for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.

Clock Controller Diagram

(Clocking Strategy for QDR-II+ using Echo Clocks CQ and CQ#)

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.

Related Files

File Title Language Size Last Updated
AN4065 QDR-II, QDR-II+, DDR-II, and DDR-II+ Design Guide.pdf English 1.18 MB 08/26/2015
AN4065 QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide (Chinsese).pdf Chinese 1.3 MB 08/01/2017
AN4065 QDR-II, QDR-II+, DDR-II, and DDR-II+ Design Guide (Japanese).pdf Japanese 1.26 MB 08/26/2015

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Related Resources

Application Notes
AN42468 - On-Die Termination for QDR(R) II+/DDR II+ SRAMs 05/28/2020
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AN80555 - 72-Mbit RH QDR®II+ Interface Controller Implementation Details 05/14/2020
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Datasheets
CY7C1302DV25: 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture 11/30/2017
CY7C1526KV18, CY7C1513KV18, CY7C1515KV18: 72-Mbit QDR® II SRAM Four-Word Burst Architecture 11/20/2017
CY7C1518KV18, CY7C1520KV18: 72-Mbit DDR II SRAM Two-Word Burst Architecture 02/13/2018
CY7C1565KV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 11/30/2017
CY7C1525KV18, CY7C1512KV18, CY7C1514KV18: 72-Mbit QDR® II SRAM Two-Word Burst Architecture 01/29/2018
CY7C1568KV18, CY7C1570KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 03/15/2016
CY7C1310JV18, CY7C1910JV18, CY7C1312JV18, CY7C1314JV18: 18-Mbit QDR® II SRAM 2-Word Burst Architecture 05/28/2020
CY7C1548KV18, CY7C1550KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C1543KV18, CY7C1545KV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C15632KV18, 72-Mbit QDR(R) II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C1523KV18: 72-Mbit DDR II SIO SRAM Two-Word Burst Architecture 01/29/2018
CY7C1521KV18, 72-Mbit DDR II SRAM Four-Word Burst Architecture 11/30/2017
CY7C1248KV18, CY7C1250KV18: 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, CY7C1415KV18 : 36-Mbit QDR® II SRAM Four-Word Burst Architecture 11/28/2017
CY7C2263KV18, CY7C2265KV18: 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/06/2016
CY7C2268KV18, CY7C2270KV18: 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/28/2020
CY7C1425KV18, CY7C1412KV18, CY7C1414KV18: 36-Mbit QDR® II SRAM Two-Word Burst Architecture 01/29/2018
CY7C1418KV18, CY7C1420KV18: 36-Mbit DDR II SRAM Two-Word Burst Architecture 01/29/2018
CY7C1268KV18, CY7C1270KV18: 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 11/29/2017
CY7C1423KV18/CY7C1424KV18, 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 01/29/2018
CY7C1243KV18/CY7C1245KV18, 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 02/13/2018
CY7C1263KV18/CY7C1265KV18, 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C1312KV18, CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 11/30/2017
CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, CY7C1315KV18: 18-Mbit QDR® II SRAM Four-Word Burst Architecture 02/13/2018
CY7C1318KV18, CY7C1320KV18: 18-Mbit DDR II SRAM Two-Word Burst Architecture 01/29/2018
CY7C1319KV18, CY7C1321KV18: 18-Mbit DDR II SRAM Four-Word Burst Architecture 01/29/2018
CY7C1392KV18, CY7C1393KV18: 18-Mbit DDR II SIO SRAM Two-Word Burst Architecture 01/29/2018
CY7C1163KV18, CY7C1165KV18: 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C1143KV18, CY7C1145KV18: 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 02/03/2016
CY7C2163KV18/CY7C2165KV18, 18-MBIT QDR(R) II+ SRAM FOUR-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) WITH ODT 05/28/2020
CY7C1148KV18, CY7C1150KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C1168KV18, CY7C1170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
CY7C25682KV18, CY7C25702KV18: 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 03/15/2016
CY7C25442KV18: 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 11/28/2017
CY7C25632KV18, CY7C25652KV18: 72-Mbit QDR®II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 11/30/2017
CY7C1623KV18: 144-Mbit DDR-II SIO SRAM Two-Word Burst Architecture 05/28/2020
CY7C1643KV18/CY7C1645KV18, 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) 11/29/2017
CY7C1648KV18, CY7C1650KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 01/29/2018
CY7C1663KV18/CY7C1665KV18, 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2663KV18, CY7C2665KV18: 144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 11/27/2017
CY7C2642KV18, CY7C2644KV18: 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 01/08/2016
CY7C1613KV18/CY7C1615KV18, 144-MBIT QDR® II SRAM FOUR-WORD BURST ARCHITECTURE 01/29/2018
CY7C1618KV18, CY7C1620KV18: 144-Mbit DDR II SRAM Two-Word Burst Architecture 12/03/2017
CY7C2670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
CY7C1625KV18, CY7C1612KV18, CY7C1614KV18: 144-Mbit QDR® II SRAM Two-Word Burst Architecture 02/15/2018
CY7C2563XV18, CY7C2565XV18: 72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 11/27/2017
CY7C1562XV18, CY7C1564XV18: 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C1568XV18, CY7C1570XV18: 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2562XV18, CY7C2564XV18: 72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 09/03/2017
CY7C1563XV18, CY7C1565XV18: 72-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 01/29/2018
CY7C2568XV18, CY7C2570XV18: 72-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 08/27/2015
CY7C1262XV18, CY7C1264XV18: 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C1263XV18, CY7C1265XV18: 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C1268XV18, CY7C1270XV18: 36-Mbit DDR II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 05/28/2020
CY7C2262XV18/CY7C2264XV18, 36-Mbit QDR(R) II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/28/2020
CY7C2263XV18, CY7C2265XV18: 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 05/28/2020
CY7C2268XV18/CY7C2270XV18, 36-MBIT DDR II+ XTREME SRAM TWO-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) WITH ODT 05/28/2020
CY7C1668KV18, CY7C1670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 12/03/2017
CYRS1542AV18, CYRS1544AV18: 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology 05/28/2020
CYRS1543AV18, CYRS1545AV18: 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture with RadStop™ Technology 05/28/2020
CY7C2245KV18: 36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 05/30/2020
CY7C25422KV18: 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 01/29/2018

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Datasheets (63)

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