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AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide | Cypress Semiconductor

AN4065 - QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide

Last Updated: 
May 14, 2020
Version: 
*I

Cypress Quad Data Rate™ (QDR®)-II, QDR-II+, DDR-II, and DDR-II+ SRAMs address the high-bandwidth requirements for networking and data storage applications that provide up to 80 GBps data transfer rate. The purpose of this application note is to assist system designers in using the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices. It includes guidelines on clocking and termination techniques for the QDR-II, QDR-II+, DDR-II, and DDR-II+ SRAM devices.

Clock Controller Diagram

(Clocking Strategy for QDR-II+ using Echo Clocks CQ and CQ#)

Dear valued customer,

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For the full version of this message, please download the PDF version.

Translated documents are for reference only. We recommend that you refer to the English-language version of a document if you are engaged in development of a design.

Related Files

File Title Language Size Last Updated
AN4065 QDR-II, QDR-II+, DDR-II, and DDR-II+ Design Guide.pdf English 1.18 MB 08/26/2015
AN4065 QDR®-II, QDR-II+, DDR-II, and DDR-II+ Design Guide (Chinsese).pdf Chinese 1.3 MB 08/01/2017
AN4065 QDR-II, QDR-II+, DDR-II, and DDR-II+ Design Guide (Japanese).pdf Japanese 1.26 MB 08/26/2015

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Related Resources

Application Notes
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CY7C1312KV18, CY7C1314KV18 18-Mbit QDR® II SRAM Two-Word Burst Architecture 11/30/2017
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CY7C2168KV18, CY7C2170KV18: 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 01/29/2018
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CY7C1618KV18, CY7C1620KV18: 144-Mbit DDR II SRAM Two-Word Burst Architecture 05/30/2021
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CY7C2268XV18/CY7C2270XV18, 36-MBIT DDR II+ XTREME SRAM TWO-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) WITH ODT 05/28/2020
CY7C1668KV18, CY7C1670KV18: 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 12/03/2017
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Related Resources

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Datasheets (63)

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