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PSoC 3 and PSoC 5 photo and block diagram | Cypress Semiconductor

PSoC 3 and PSoC 5 photo and block diagram

Last Updated:

September 14, 2009

Cypress's two newest architectures in its PSoC® programmable system-on-chip line dramatically increase performance and lower power, opening new markets to the revolutionary PSoC technology across 8-, 16-, and 32-bit applications. The PSoC 3 architecture is based on a high-performance 8-bit 8051 processor with up to 33 MIPS, while the PSoC 5 architecture includes a powerful 32-bit ARM Cortex-M3 processor with up to 100 DMIPS. These new architectures have been designed to meet the demands of extremely low power applications by delivering the industry’s widest voltage range down to 0.5V along with low 200 nA hibernate current.  PSoC 3 and PSoC 5 are powered by the new revolutionary PSoC Creator™ design software providing designers with a seamless, programmable design platform.

The new PSoC 3 and PSoC 5 architectures extend the world’s only programmable analog and digital embedded design platform delivering unmatched time-to-market, integration, and flexibility.  These architectures include high-precision, programmable analog resources that can be configured as ADCs, DACs, TIAs, Mixers, PGAs, OpAmps, and more.  They also include enhanced programmable-logic based digital resources that can be configured as 8-, 16-, 24- and 32-bit Timers, Counters, and PWMs, as well as more advanced digital peripherals such as Cyclic Redundancy Check (CRC), Pseudo Random Sequence (PRS) generators, and Quadrature decoders. Designers have a unique ability to customize this digital system through full featured general purpose PLD-based logic available in PSoC 3 and PSoC 5. All of the peripherals and APIs are common between PSoC 3 and PSoC 5 architectures, enabling seamless migration between 8-, 16- and 32-bit applications.

Click the download links below for a high-resolution image and block diagram of the architectures.