|QDR-IV XP||QDR-IV HP|
|Operating Frequency (Max)||1066 MHz||667 MHz|
|Random Transaction Rate (RTR)||2132 MT/s||1334 MT/s|
|Read Latency||8 cycles||5 cycles|
|Write Latency||5 cycles||3 cycles|
|Density||144 Mb, 72 Mb|
|Data Width||x18, x36|
|Burst Length||2 Words|
|Core Voltage||1.30 V|
HSTL/SSTL: 1.2 V, 1.25 V
POD: 1.1 V, 1.2 V
|Temperature Classification||Commercial. (For availability in Industrial and Military Grade contact email@example.com)|
The QDR Advantage
Cypress QDR SRAM provides fully
random memory access
The QDR SRAM architecture provides the random memory access capabilities needed for networking and other high performance applications. In these applications, memory is a major bottleneck to reaching higher system performance. For example, in networking applications, each data packet requires several random memory transactions. Therefore, the packet processing rate of the system is dependent on how quickly the system can access memory. Cypress’s QDR SRAM provides the RTR necessary to break system bottlenecks and reach higher performance.
Other memory technologies are optimized for high density. They do not meet the needs of high performance applications that demand high RTR. QDR SRAM, on the other hand, is designed specifically for maximum RTR. QDR SRAM allows access to any two memory locations on every clock cycle, and performance never depends on which memory location was accessed in the previous clock cycle. With QDR SRAM, RTR is guaranteed.
Cypress’s QDR-IV SRAM provides RTR up to 2132 MT/s. This level of performance is critical to enable the next generation of high performance systems.
Cypress QDR-IV SRAM offers several new features which have been engineered to solve the challenges of next generation high performance systems.
QDR-IV SRAM provides two independent, bidirectional DDR data ports. These two ports can be accessed concurrently and operate independently. Each port can be used for read and write operations, which allows QDR-IV to support unbalanced read/write workloads. Access to each port is provided through a common address bus.
QDR-IV SRAM implements on-chip ECC error detection and correction circuitry to provide data integrity. All single-bit memory errors, including those caused by cosmic rays and alpha particles, are detected and corrected by the on-chip circuitry. The resulting soft error rate (SER) is expected to be less than 0.01 FITs/Mb. QDR-IV offers a programmable address parity feature to provide integrity on the address bus.
Reduces switching noise and power consumption
Improves signal capture timings at high frequencies
QDR-IV SRAM supports POD (pseudo open drain) signaling at 1.1 V or 1.2 V and HSTL/SSTL compatible signaling at 1.2 V or 1.25 V. The signaling interface type and voltage are user programmable. Interface flexibility provides interoperability with a variety of host processors.
Faster RTR and higher operating frequency
QDR-IV XP SRAM contains a memory array divided into eight banks. Banking enables faster RTR and higher operating frequencies. Each of the two ports can access one bank per clock cycle, as long as both ports don’t access the same bank in the same cycle. QDR-IV is also available without banking operation (HP version).
On-Die Termination improves signal integrity, saves board space, and reduces cost compared to external termination resistors. In high speed systems without proper signal termination, electrical signals are reflected when they reach the end of a transmission path, producing noise that lowers signal quality and reduces performance. These reflections can be reduced by attaching a resistor to the end of the transmission line. However, external resistors consume board space, complicate board routing, and increase cost. ODT addresses these challenges by embedding the termination resistors within the SRAM die, which provides proper signal termination and enables high speed signaling without adding external components. With QDR-IV, ODT is programmable for clock, address/command, and data inputs.