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Traveo S6J351C Auto Standard ARM® Cortex®-R5 MCU | Cypress Semiconductor

Traveo S6J351C Auto Standard ARM® Cortex®-R5 MCU

The Traveo™ family expands automotive applications, scalability and performance into one line-up and at the same time adds new features to fulfill the latest requirements of the automotive industry.

Based on the powerful ARM® Cortex®-R5 and R5F core in single and dual core operations, this family offers state-of-the-art, real-time performance, safety and security features. The family supports the latest in-car networks and offers high performance graphics engines optimized for a minimum memory footprint and embeds dedicated features to increase data security in the car.

The Traveo™ MCU family S6J351C features 32-bit RISC microcontrollers with an ARM® Cortex®- R5F core and operates up to 132MHz. This microcontroller comes with high performance, 2MB of high density embedded Flash and four channels of CAN FD interface for Body control applications.

Features

  • Single-chip solution for automotive body control modules
  • CAN FD, twelve channels of multi-functional serial and two channel of high-speed DDR Quad SPI allow fast communication for various of in-vehicle communication
  • ARM® Cortex® R5F@132MHz, offering about 220MIPS

Block Diagram

Traveo S6J351 Series Block Diagram

Product Name Maximum Internal Clock [MHz] Floating Point Unit Memory Protection Unit Package [pin] Operating Voltage: VCC [V] Sub Clock ROM [Byte] RAM [Byte] Cache [KByte] DMAC [ch] Ext. Interrupt [ch] External Bus I/F Max. I/O port [ch] 12-bit ADC [ch x unit] Output Compare [ch] Free-Run Timer [ch] Input Capture [ch] Reload Timer, PWM Timer, PWC Timer, PPG Timer / Base Timer (Reload/PPG/PWM/PWC Selectable) [ch] Up/Down Counter [ch] Other timers [ch] I2C, UART/SI, SIO, Multi Function Serial - MFS (MFS: LIN/UART/SIO/I2C Selectable) [ch] CAN [ch] MediaLB Ethernet AVB LCD Controller Driver
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Stepper Motor Controller Driver [ch] Graphic Display Controller Display Output [ch] FPD Link (LVDS) [ch] Sound Generator High-Quality Sound System Secure Hardware Extention (Optional) Remarks Evaluation Method / Device
S6J351CJ 132 Yes Yes TEQFP-176 5.0 or 3.3
(Combination)
Yes 2112K + 112K TC- RAM: 128K, System- RAM: 128K
Backup- RAM: 16+8K
Instruction: 16
Data: 16
16 24 - 126 48 12 (Output x 12) 8 (Input x 8) 12 Reload Timer x 6, Base Timer x 16 (32-ch) 2 * RTC x 1 MFS x 12 (I2C x 10, 400k x 2) CANFD 128Msg-buffer x 4 - - - 5 - Yes ARM Cortex-R5F, Quad-SPI x 2-ch,
Partial Wakeup (Analog x 8, Trigger x 1)
On-chip Debugger
S6J351CH 132 Yes Yes TEQFP-144 5.0 or 3.3
(Combination)
Yes 2112K + 112K TC- RAM: 128K, System- RAM: 128K
Backup- RAM: 16+8K
Instruction: 16
Data: 16
16 24 - 94 40 12 (Output x 12) 8 (Input x 8) 12 Reload Timer x 6, Base Timer x 16 (32-ch) 2 * RTC x 1 MFS x 12 (I2C x 10, 400k x 2) CANFD 128Msg-buffer x 4 - - - 5 - Yes ARM Cortex-R5F, Quad-SPI x 2-ch,
Partial Wakeup (Analog x 8, Trigger x 1)
On-chip Debugger