Cypress QDR-IV SRAM offers several new features which have been engineered to solve the challenges of next generation high performance systems.
Two Bidirectional Data Ports
High transaction rates for any mix of read/write operations
QDR-IV SRAM provides two independent, bidirectional DDR data ports. These two ports can be accessed concurrently and operate independently. Each port can be used for read and write operations, which allows QDR-IV to support unbalanced read/write workloads. Access to each port is provided through a common address bus.
Built-in error correction provides data integrity and virtually eliminates soft errors
QDR-IV SRAM implements on-chip ECC error detection and correction circuitry to provide data integrity. All single-bit memory errors, including those caused by cosmic rays and alpha particles, are detected and corrected by the on-chip circuitry. The resulting soft error rate (SER) is expected to be less than 0.01 FITs/Mb. QDR-IV offers a programmable address parity feature to provide integrity on the address bus.
Reduces switching noise and power consumption
QDR-IV SRAM provides address and data bus inversion to reduce simultaneous switching noise and I/O power consumption. With this feature, the number of 0’s and 1’s in every data word or address are counted just prior to transfer. If more than half the pins in the group are 0’s, then the bus is inverted and the inversion pin is set. Bus inversion ensures that no more than half of the pins switch between transfers. Less pin switching reduces noise and power consumption. This feature is programmable and can be enabled or disabled for the address and data bus independently.
Deskew Training Sequence
Improves signal capture timings at high frequencies
QDR-IV SRAM provides a training sequence for per-bit deskew. Deskew training allows for optimal signal capture when operating at high frequencies.
POD and HSTL/SSTL Signaling Interface
Programmable interfaces provide flexibility
QDR-IV SRAM supports POD (pseudo open drain) signaling at 1.1 V or 1.2 V and HSTL/SSTL compatible signaling at 1.2 V or 1.25 V. The signaling interface type and voltage are user programmable. Interface flexibility provides interoperability with a variety of host processors.
Faster RTR and higher operating frequency
QDR-IV XP SRAM contains a memory array divided into eight banks. Banking enables faster RTR and higher operating frequencies. Each of the two ports can access one bank per clock cycle, as long as both ports don’t access the same bank in the same cycle. QDR-IV is also available without banking operation (HP version).
On-Die Termination (ODT)
Saves board space and improves signal integrity
On-Die Termination improves signal integrity, saves board space, and reduces cost compared to external termination resistors. In high speed systems without proper signal termination, electrical signals are reflected when they reach the end of a transmission path, producing noise that lowers signal quality and reduces performance. These reflections can be reduced by attaching a resistor to the end of the transmission line. However, external resistors consume board space, complicate board routing, and increase cost. ODT addresses these challenges by embedding the termination resistors within the SRAM die, which provides proper signal termination and enables high speed signaling without adding external components. With QDR-IV, ODT is programmable for clock, address/command, and data inputs.