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QDR-IV | Cypress


Introducing QDR-IV

Cypress, the worldwide leader in SRAM, now offers QDR-IV, the newest and highest performing member of the consortium-defined QDR® product line. Cypress QDR-IV SRAM provides random transaction performance that is orders of magnitude greater than commodity memories and 2.4x greater than the previous generation of QDR. QDR-IV brings a number of new features to the QDR product line, including on-chip ECC and bidirectional data ports. The QDR-IV family includes two members: QDR-IV Xtreme Performance (XP) and QDR-IV High Performance (HP).

Cypress QDR-IV is the highest performing standardized networking memory, and is ideally suited for next generation networking, communication, and high performance computing systems.


Random Transaction Rate (RTR)

Random Transaction Rate (RTR) is the number of fully random read or write transactions a memory can perform every second. It is measured in MT/s, or mega transactions per second. RTR is a critical metric in high performance applications, such as networking, where memory access is unpredictable.

  1. Download the QDR-IV SRAM Design Guide
  2. Download the Memory Controller Overview for 28-nm FPGAs:Xilinx Memory Controller Product Overview for QDR-IV:
  3. Contact Sales for the Cypress QDR-IV Memory Controller Design Guide for 28-nm FPGAs and Altera and Xilinx for 20-nm FPGA Support
  4. Download the QDR-IV Datasheets
Operating Frequency (Max) 1066 MHz 667 MHz
Random Transaction Rate (RTR) 2132 MT/s 1334 MT/s
Read Latency 8 cycles 5 cycles
Write Latency 5 cycles 3 cycles
Density 144 Mb, 72 Mb
Data Width x18, x36
Burst Length 2 Words
Package 361-ball FCBGA
ODT Yes (Programmable)
Core Voltage 1.30 V
Interface (Programmable) HSTL/SSTL: 1.2 V, 1.25 V
POD: 1.1 V, 1.2 V
Temperature styleification Commercial. (For availability in Industrial and Military Grade contact

The QDR Advantage

Cypress QDR SRAM provides fully
random memory access

The QDR SRAM architecture provides the random memory access capabilities needed for networking and other high performance applications. In these applications, memory is a major bottleneck to reaching higher system performance. For example, in networking applications, each data packet requires several random memory transactions. Therefore, the packet processing rate of the system is dependent on how quickly the system can access memory. Cypress’s QDR SRAM provides the RTR necessary to break system bottlenecks and reach higher performance.

Other memory technologies are optimized for high density. They do not meet the needs of high performance applications that demand high RTR. QDR SRAM, on the other hand, is designed specifically for maximum RTR. QDR SRAM allows access to any two memory locations on every clock cycle, and performance never depends on which memory location was accessed in the previous clock cycle. With QDR SRAM, RTR is guaranteed.

Cypress’s QDR-IV SRAM provides RTR up to 2132 MT/s. This level of performance is critical to enable the next generation of high performance systems.

Feature Summary

Cypress QDR-IV SRAM offers several new features which have been engineered to solve the challenges of next generation high performance systems.

Two Bidirectional Data Ports

High transaction rates for any mix of read/write operations

QDR-IV SRAM provides two independent, bidirectional DDR data ports. These two ports can be accessed concurrently and operate independently. Each port can be used for read and write operations, which allows QDR-IV to support unbalanced read/write workloads. Access to each port is provided through a common address bus.

On-Chip ECC

Built-in error correction provides data integrity and virtually eliminates soft errors

QDR-IV SRAM implements on-chip ECC error detection and correction circuitry to provide data integrity. All single-bit memory errors, including those caused by cosmic rays and alpha particles, are detected and corrected by the on-chip circuitry. The resulting soft error rate (SER) is expected to be less than 0.01 FITs/Mb. QDR-IV offers a programmable address parity feature to provide integrity on the address bus.

Bus Inversion

Reduces switching noise and power consumption

QDR-IV SRAM provides address and data bus inversion to reduce simultaneous switching noise and I/O power consumption. With this feature, the number of 0’s and 1’s in every data word or address are counted just prior to transfer. If more than half the pins in the group are 0’s, then the bus is inverted and the inversion pin is set. Bus inversion ensures that no more than half of the pins switch between transfers. Less pin switching reduces noise and power consumption. This feature is programmable and can be enabled or disabled for the address and data bus independently.

Deskew Training Sequence

Improves signal capture timings at high frequencies

QDR-IV SRAM provides a training sequence for per-bit deskew. Deskew training allows for optimal signal capture when operating at high frequencies.

POD and HSTL/SSTL Signaling Interface

Programmable interfaces provide flexibility

QDR-IV SRAM supports POD (pseudo open drain) signaling at 1.1 V or 1.2 V and HSTL/SSTL compatible signaling at 1.2 V or 1.25 V. The signaling interface type and voltage are user programmable. Interface flexibility provides interoperability with a variety of host processors.

Banking Operation

Faster RTR and higher operating frequency

QDR-IV XP SRAM contains a memory array divided into eight banks. Banking enables faster RTR and higher operating frequencies. Each of the two ports can access one bank per clock cycle, as long as both ports don’t access the same bank in the same cycle. QDR-IV is also available without banking operation (HP version).

On-Die Termination (ODT)

Saves board space and improves signal integrity

On-Die Termination improves signal integrity, saves board space, and reduces cost compared to external termination resistors. In high speed systems without proper signal termination, electrical signals are reflected when they reach the end of a transmission path, producing noise that lowers signal quality and reduces performance. These reflections can be reduced by attaching a resistor to the end of the transmission line. However, external resistors consume board space, complicate board routing, and increase cost. ODT addresses these challenges by embedding the termination resistors within the SRAM die, which provides proper signal termination and enables high speed signaling without adding external components. With QDR-IV, ODT is programmable for clock, address/command, and data inputs.