PSoC® 3 | Cypress

PSoC® 3

PSoC® 3 is a true programmable embedded system-on-chip integrating configurable analog and digital peripheral functions, memory and a microcontroller on a single chip. And now our breakthrough new PSoC 3 architecture boosts performance through:

  • Integrated high-precision 20-bit resolution analog
  • Ultra low power with industry’s widest voltage range
  • Programmable PLD-based logic
  • Single-Cycle 8051 core up to 67 MHz

PSoC 3 is now available in Chip Scale Packages (CSP) allowing you to design with the flexibility of PSoC in space constrained and small form factor applications like wearables, fitness products, and mobile devices.


The CY8C32 family of ultra low power, PSoC® programmable system-on-chip devices is part of the scalable 8-bit PSoC 3 and 32-bit PSoC 5 architectures.
The CY8C34 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. 
The CY8C36 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem.
The CY8C38 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility.

Design support

  1. Watch the PSoC 3 and PSoC 5: Introduction to the architecture and design flow video.
  2. Download PSoC Creator
    • Quick Start Guide available within the tool (Help → Documentation → Quick Start Guide)
    • View tutorial video inside of PSoC Creator
  3. Purchase a CY8CKIT-030 PSoC 3 Development Kit.
  4. Start your first PSoC designs
  5. Join the Cypress Developer Community.
Device Documentation
Family Datasheet
The family datasheet is intended to provide quick reference on the specific PSoC 3 device family.
Family Programming Specifications
This document (available as an application note) provides information on hardware connections for programming, programming vectors required to develop your own PSoC 3 Programmers.
Technical Reference Manual
The PSoC 3 Technical Reference Manual provides detailed information on the device features and how they work. It is intended for advance user's who want to understand what's going on under the hood.
Software Documentation
Self Help Documentation

The PSoC® architecture consists of configurable analog and digital blocks, a CPU subsystem and programmable routing and interconnect. PSoC lets you plug in predefined and tested IP from the PSoC library of functions, or code your own. Either way, you have the flexibility to build innovation and competitive advantage into your products.


Programable Routing & Interconnect

This frees you to re-route signals to userselected pins, shedding the constraints of a fixed-peripheral controller. In addition, global buses allow for signal multiplexing and logic operations, eliminating the need for a complicated digital-logic gate design.


Configurable Analog and Digital Blocks

The union of configurable analog and digital circuitry is the basis of the PSoC platform. You configure these blocks using pre-built library functions or by creating your own. By combining several digital blocks, you can create 16-, 24-, or even 32-bit wide logic resources. The analog blocks are composed of an assortment of switch capacitor, op-amp, comparator, ADC, DAC, and digital filter blocks, allowing complex analog signal flows. For a partial list of preconfigured functions included in PSoC software, see the sidebars on the next two pages. You can modify and personalize each function to your design.


CPU Subsystem

PSoC offers a sophisticated CPU subsystem with SRAM , EE PROM, and flash memory, multiple core options and a variety of essential system resources including:

• Internal main and low-speed oscillator

• Connectivity to external crystal oscillator for precision, programmable clocking

• Sleep and watchdog timers

• Multiple clock sources that include a PLL

PSoC devices also have dedicated communication interfaces like I2C, Full-Speed USB 2.0, CAN 2.0, and on-chip debugging capabilities using JTAG and Serial Wire Debug. The newest members of the PSoC family offer industry-standard processors like the 8051 and ARM Cortex-M3.

Low Power Management Solutions with PSoC 3 and PSoC 5 devices are easy to design and implement because both families were designed for power optimization. PSoC 3 and PSoC 5 devices have flexible power modes to optimize power and performance.

  • Best-in-class low power specifications plus industry leading CPU speed
  • World’s widest voltage range, the only device that offers full analog capability below 1.8V
  • Minimizes power by offloading CPU processing using on-chip programmable logic
  • Integrated peripherals reduce total system level power
  • PSoC Creator software provides easy to use APIs for quick power management
  • Wide operating voltage range: 0.5V to 5.5V
  • 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, 6.6 mA at 48 MHz
  • 1 µA sleep mode with real-time clock and low voltage detect (LVD) interrupt
  • 200 nA hibernate mode with SRAM retention


Sleep Modes Wake-up Time Power (typ) Code Execution Digital Resources Analog Resources Clock Sources Available Wakeup Sources Reset Sources
Active - 1.2mA Yes All All All - All
Alternate Active - TBD User Defined All All All - All
Sleep <15µs 1µA No I2C Comparator ILO/kHzECO Comparator,
Hibernate <100µs 200nA No None None None PICU XRES


Full Analog Performance Across the Entire Voltage Range

PSoC 3 and PSoC 5 are the only devices on the market to offer full analog performance down to 0.5V allowing you to not only operate off of a single cell battery, but also a solar cell.