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PLL/SSCG ICs | Cypress Semiconductor


PLL Frequency Synthesizer IC

These are built in dual modulus pre-scaler, adaptable from 50MHz to 3GHz and it can make up low noise small serial input Phase Locked Loop (PLL) frequency enabling pulse swallowing operation.

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  • Built-in dual modulus pre-scaler correspond to wide frequency range of 50MHz to 3GHz.
  • Pre-scaler divide ratio: 8/16/32/64/128(depends on individual product)
  • Built-in direct power saving function
  • Serial input programmable reference counter, swallow counter and programmable counter
  • Built-in high-speed tuning, low-noise phase comparator, constant current charge pump circuit
  • On-chip phase control for phase comparator
  • Built-in digital locking detector circuit to detect PLL locking and unlocking


SSCG (Spread Spectrum Clock Generator)

Electro Magnetic Interference becomes a problem with the speed-up/high-density of electronic hardware. When the clock generator in an electronic hardware outputs the single frequency, radiation at the frequency and high-frequency becomes large. SSCG can suppress the peak lower by oscillation with slightly modulated frequency (Frequency modulation).

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  • SSCG suppresses unnecessary radiation, and is effective not only for the oscillation frequency of clock (basic wave) but also higher harmonic wave.
  • Low cost & downsizing: Usage of components like bypass capacitor, choke coil, ferrite bead and shield parts etc. can be reduced, thus reducing the total development cost.
  • Reducing man-hour: If the architecture of the design is processed on the basis that SSCG is mounted at the early planning stages, then the repeated simulation-evaluation-analysis cycle gets reduced drastically.

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