MB966B0 | Cypress Semiconductor

MB966B0

MB96600 series is based on Cypress' advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new 16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time.

For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with excellent EMI behavior. The emitted power is minimised by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed.

Product Name Maximum Internal Clock [MHz] Floating Point Unit Memory Protection Unit Package [pin] Operating Voltage: VCC[V] Sub Clock Memory Type ROM [Byte] RAM [Byte] Cache [KByte] DMAC [ch] Ext. Interrupt [ch] External Bus I/F Max. I/O port [ch] 10-bit ADC [ch x unit] 12-bit ADC [ch x unit] DAC [ch] Output Compare [ch] Free-Run Timer [ch] Input Capture [ch] Reload Timer, PWM Timer, PWC Timer, PPG Timer / Base Timer (Reload/PPG/PWM/PWC Selectable) [ch] Up/Down Counter [ch] Other timers [ch] Three-phase Inverter Support I2C, UART/SI, SIO, Multi Function Serial - MFS (MFS: LIN/UART/SIO/I2C Selectable) [ch] LIN/UART/SIO [ch] CAN [ch] FlexRay [unit] MediaLB Ethernet AVB LCD Controller Driver [seg x com] Stepper Motor Controller Driver [ch] Graphic Display Controller Sound Generator Resolver to Digital Converter Secure Hardware Extention Remarks Evaluation Method / Device
MB96F6B5A 32 - - LQFP-100 2.7 to 5.5 Yes Dual Op. Flash 128.5K + 32K 8K - 4 16 - 79 (Single clock) 77 (Dual clock) 27 x 1 - - 4 2 6 Reload Timer 5 + PPG 8bit x 16 + 16bit x 12 - QPRC x 2 - I2C x 1 5 - - - - 36 x 4 - - 2 - - Option without CAN On-chip Debug
MB96F6B5R 32 - - LQFP-100 2.7 to 5.5 Yes Dual Op. Flash 128.5K + 32K 8K - 4 16 - 79 (Single clock) 77 (Dual clock) 27 x 1 - - 4 2 6 Reload Timer 5 + PPG 8bit x 16 + 16bit x 12 - QPRC x 2 - I2C x 1 5 1 - - - 36 x 4 - - 2 - - Option without CAN On-chip Debug
MB96F6B6R 32 - - LQFP-100 2.7 to 5.5 Yes Dual Op. Flash 256.5K + 32K 16K - 4 16 - 79 (Single clock) 77 (Dual clock) 27 x 1 - - 4 2 6 Reload Timer 5 + PPG 8bit x 16 + 16bit x 12 - QPRC x 2 - I2C x 1 5 1 - - - 36 x 4 - - 2 - - Option without CAN On-chip Debug

Hardware

Name Part number Description Remarks
Main unit MB2100-01A-E / Details Single wire On-chip Debugger Main unit
Order P/N: MB2100-01A-E-SPN
 
Evaluation board MB2198-760-E Main board for MB96600
Order P/N: MB2198-760-E-SPN
Option
MB2198-764-04-E Sub board for MB966B0
(MB96F6B6R is mounted, without socket)

 

Software

Software Part number
SOFTUNE V3 Professional Pack SP3607Z008-P01

CPU Information file: Supported
Sample I/O register file: Supported