MB96690 | Cypress Semiconductor
MB96600 series without external bus interface is based on Cypress' advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). Thus an easy migration of MB96300 software to the MB96600 products is possible. New feature like the single wire on-chip debugging facilitate the software development in comparison to the previous series MB96300.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 32MHz operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 31.25ns going together with excellent EMI behavior. The emitted power is minimised by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select suitable operation frequencies for peripheral resources independent of the CPU speed.