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DDR-II+ CIO | Cypress Semiconductor


The DDRII SRAMS are similar to DDRII SRAMs in their operation but with additional performance improvements. The redundant data input clocks  (C & /C) are not present in the DDRII suite of products. Instead DDRII SRAMs include a hand shake signal (QVLD) that indicates when the Data will become valid thereby simplifying data capture. The customers also have the choice of QDRII products with programmable ODT (On Die Termination). The ODT feature turns on during a write cycle and turns off during a read cycle to save power. The DDRII SRAMs have a maximum speed of 550MHz with read latencies of either 2 cycles or 2.5 cycles, with a burst length of 2 and are available in an industry standard 165 Ball BGA.