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DDR-II CIO | Cypress Semiconductor


The DDRII SRAMs are similar to DDR SRAMs in their operation but with some performance improvements. The DDRII SRAMs include source synchronous free running echo clocks (CQ, /CQ) that enable customers to easily capture data. The DDRII SRAMs also support 1.5V HSTL interface. The applications are the same as that of DDR SRAMs. The DDRII SRAMs have a maximum speed of 333MHz with a read latency of 1.5 cycles, with burst lengths of 2 and 4, and are available in an industry standard 165 Ball BGA.

  1. Download the DDR-II SRAM Design Guide
  2. Download the DDR-II Datasheets