CY8C21x34/B | Cypress Semiconductor


The PSoC family consists of many Mixed-Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one low cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture enables the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IOs are included in a range of convenient pinouts. The PSoC architecture consists of four main areas: the Core, the System Resources, the Digital System, and the Analog System. Configurable global bus resources allow combining all the device resources into a complete custom system.

Each CY8C21x34/B device includes four digital blocks and four analog blocks. Depending on the package, up to 28 general purpose IOs (GPIO) are also included. The GPIO provide access to the global digital and analog interconnects.

Block Diagram


The CY8C21x34B device supports CapSense as well.  CapSense is ideal for proximity sensing and water tolerant designs. Enabled with SmartSense™ Auto-tuning, this family is easy to use and significantly reduces the design cycle time by eliminating the tuning process throughout the entire product development cycle from prototype to mass production. SmartSense tunes each CapSense sensor automatically at power up and then monitors and maintains optimum sensor performance during run time. This technology adapts for manufacturing variation in PCBs, overlays and noise generators such as LCD inverters, AC line noise and switch mode power supplies and automatically tunes them out.