You are here

Async SRAM with ECC | Cypress Semiconductor

Async SRAM with ECC

Introducing Fast Asynchronous SRAM with ECC

Cypress, the world leader in SRAMs, now offers Asynchronous SRAMs with ECC, the latest member of its Asynchronous SRAM product family. With the performance to serve a wide variety of industrial, communication, data processing, medical, consumer and military applications, Fast and Micropower (MoBL®) SRAM devices are form-fit-function compatible with existing Asynchronous SRAM devices based on older technology nodes. This allows you to improve system reliability without investing in PCB re-design.

Asynchronous SRAM with ECC Highlights


  • High reliability: Soft-Error Rate < 0.1FIT/Mbit
  • ERR pin to indicate single-bit errors
  • Density options: 4-Mbit, 16-Mbit
  • Fast access time: 10ns (FAST)
  • Ultra low standby current: 8.7μA (4-Mbit MoBL®)
  • Deep Sleep current of 15μA at an access time of 10ns (4-Mbit FAST with PowerSnooze™)
  • Bus-width configurations: x8, x16 and x32
  • Wide operating voltage range: 1.8-5.0V
  • Industrial and Automotive temperature grades
  • Industry-standard, RoHS-compliant packages
  • Form-fit-function compatible with existing ASYNC SRAM devices




4-Mbit Micropower (MoBL®) Asynchronous SRAM with ECC

4-Mbit Fast Asynchronous SRAM with ECC

4-Mbit Fast Asynchronous SRAM with PowerSnooze™ & ECC

Memory for wide variety of applications

Asynchronous SRAMs with ECC are suitable for a wide variety of industrial, medical, commercial, automotive and military applications that require the highest standards of reliability and performance. Fast SRAMs are an ideal choice in networking applications such as switches and routers, IP-phones, test equipment and automotive electronics. MoBL® SRAMs are used in high-performance, battery powered and battery-backed solutions across a range of application segments, like PLCs, Multifunction Printers and Implantable medical devices.


Industrial controllers

Asynchronous SRAM devices are used in Programmable Logic Controllers (PLC) designs for backup of critical tool position and operation data that needs to be secured through power interruptions. Power-backup is provided by either a battery or a Super-Capacitor.

Battery Backed Application

Click to Enlarge


The key requirements of industrial controllers are reduced power consumption and lower soft error rate. In industrial controllers, soft errors result in malfunction at startup due to corrupted setup information, leading to system failures.



Router designs use SRAM in a battery backed configuration for permanent storage of startup configuration. This data is user modifiable, and is critical for the proper functioning of the device. The SRAM is also used for permanent storage of hardware revision, identification information and Media Access Control (MAC) addresses for LAN interfaces. An unrecoverable soft error can play havoc with things like traffic destinations in networking equipment. 

A commonly used configuration is shown in the schematic included in Figure below, which shows how a MoBL® SRAM is used in a battery-backed configuration with a Supervisory chip.

Battery Backed Application
Click to Enlarge


Multi-Functional printers

Multi function printers (MFP) are a primary application segment for MoBL® SRAM devices. A wide variety of data is stored in MFP memory both permanently and temporarily. A Hard Disk Drive (HDD) or a Flash Drive store various types of user information, while user tool settings, network settings, and configuration data is stored in a dedicated MoBL® SRAM. The SRAM is also used for Job status and Font tables. The data is critical to the operation of the device, and is protected through power cycles with a battery. Hence MFP designs require SRAMs with high reliability and low error rates.

Battery Backed Application
Click to Enlarge

Complete Freedom from Soft-Errors

The latest generation Asynchronous SRAMs from Cypress make the best of an advanced process technology by integrating single-bit error correction capability and bit-interleaving techniques to mitigate the effects of soft errors. All single-bit memory errors, including those caused by cosmic rays and alpha particles, are detected and corrected by the on-chip circuitry.


How it works

These latest generation devices use Hamming Code algorithm for single-bit error detection and correction. A hardware ECC block performs all ECC-related functions in line, without user intervention and without affecting the access time performance of the device. The single-bit error detection and correction capability is supplemented by a 16-bit interleaving scheme to avoid the occurrence of multi-bit errors. Together, these features provide significant improvement in soft error rate (SER) performance, resulting in FIT rates of less than 0.1 FIT/Mbit.


Enhanced Reliability with ERR Pin

Over a period of time, multiple single event upsets (SEUs) may affect the same word, resulting in an accumulated multi-bit upset (two or more single-bit upsets in the same word). To mitigate this problem, these devices include an optional error indication (ERR) pin. During read operation, the ERR pin indicates detection and correction of a single-bit error at the accessed memory location. The system can use this information to recognize a single-bit error and refresh memory to avoid accumulation of single bit errors.


Fast SRAM with PowerSnooze™

A new Fast SRAM that combines the 10ns access times of Fast SRAMs with low standby power comparable to that of the MoBL® family. PowerSnooze is an additional power-saving deep-sleep mode that achieves 12 uA (typical) deep-sleep current for a 16Mb SRAM. The 16 Mb Fast SRAM with PowerSnooze also offers on-chip ECC.

4MB Asynchronous SRAM with ECC

Click to view 4MB Asynchronous SRAM with ECC Quick Presentation in full screen

Solution Example Asynchronous SRAM with ECC

Click to view Asynchronous SRAM with ECC Solution Example in full screen