Processes

Cypress has a wide variety of process platforms to choose from, each with a number of process options for metal layers, FET characteristics, NVM, and passive components.

Design Rule (nm)	90	130	180	250	350
# Layers Metal	3-5	3-6	3-4	3-4	2-3
SAC contact	Y	Y	Y	Y	Y
Low-power SRAM	Y	Y	Y	Y
Isolation	STI	STI	STI	sr-LOCOS	sr-LOCOS
Gate	W-clad Poly	Poly	Poly	Poly	Poly
SONOS NVM		Y*			Y*
NPN CMOS				Y*
Capacitor		Y*		Y*
Precision Resistor		Y*		Y*
Inductor		Y*
OTP		Y*
Polyimide	Y*	Y*	Y*	Y*
Dual-Damascene Interconnect	Y*

                               *AVAILABLE AS AN OPTION

Design kits and standard cell IP libraries will be made available to customers, and higher level IP blocks are available for licensing.