CY7C53120E2-10SXI | Cypress Semiconductor

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CY7C53120E2-10SXI
Status: In Production

Datasheet

(pdf, 539.48 KB) RoHS PB Free

CY7C53120E2-10SXI

Automotive QualifiedN
Flash (KB)2
Max. Input Clock (MHz)10
Max. Operating Temp. (°C)85
Max. Operating Voltage (V)5.00
Min. Operating Temp. (°C)-40
Min. Operating Voltage (V)5.00
ROM (KB)10
Tape & ReelN

Pricing & Inventory Availability

1-9 unit Price* 10-24 unit Price* 25-99 unit Price* 100-249 unit Price* 250-999 unit Price* 1000+ unit Price*
$13.11 $12.56 $12.01 $11.46 $10.91 $9.99
Availability Quantity Ships In Buy from Cypress Buy from Distributors
In Stock 139 24-48 hours

Packaging/Ordering

Package
No. of Pins
32
Package Dimensions
810 L x 0 H x 450 W (Mils)
Package Weight
1 340.00 (mgs)
Package Cross Section Drawing
Package Carrier
TUBE
Package Carrier Drawing / Orientation
Standard Pack Quantity
875
Minimum Order Quantity (MOQ)
875
Order Increment
875
Estimated Lead Time (days)
126
HTS Code
8542.31.0001
ECCN
None
ECCN Suball
EAR99

Quality and RoHS

Moisture Sensitivity Level (MSL)
3
Peak Reflow Temp. (°C)
PB Free
Y
Lead/Ball Finish
Ni/Pd/Au

Package Material Declaration

Device Qualification Reports

FIT/MTBF, ESD (HBM/CDM) and Latch-up data available in the Device Qualification Report.

Last Update: May 15, 2013

Technical Documents

Application Notes (1)

Product Change Notice (PCN) (13)

Nov 09, 2017
Planned Qualification of Spansion Manufacturing Sites for Cypress Products
Oct 31, 2017
Q2, 2012 - Q4, 2013 Horizon Report
Oct 30, 2017
Q1, 2012 - Q2, 2013 Horizon Report
Oct 25, 2017
Qualification of Copper Palladium Wire Bonds for Select Lead Frame Products at JCET China
Oct 24, 2017
Transfer of package manufacturing from Cypress Philippines to Jiangsu Changjiang Electronics Technology Co., Ltd. (JCET) for select products
Oct 18, 2017
Qualification of Cypress Minnesota as Alternate Wafer Fabrication Facility for Neuron® Chip Network Processor Products
Oct 17, 2017
Changes to Minimum Order Quantity (MOQ) and Order Increment (OI) values on various Cypress Products
Oct 16, 2017
Shipping Label Upgrade
Oct 13, 2017
Change in Tube Bundling Ship Process
Oct 13, 2017
Add Alternate Assembly Site for SOIC150mils Pb-Free
Oct 12, 2017
Correction to Affected Devices in PCN#071577: Qualification of 0.9-mil Au wire diameter for CCD and MID devices assembled at CML
Oct 12, 2017
Qualification of KEG6000DA and KEG3000DA Green Mold Compound for 32 leads, Lead-free and standard, 450 mil body size, SOIC Packages Assembled at Cypress
Oct 12, 2017
Qualification of 0.9-mil Au wire diameter for CCD and MID devices assembled at CML

Advanced Product Change Notice (APCN) (2)

Oct 30, 2017
Advance Notification - Planned Changes to MoBL-USB TX3LP18
Oct 30, 2017
Advance Notification - Transfer of Specific Product Manufactured by Cypress Semiconductor Texas to Cypress Manufacturing Minnesota

Product Information Notice (PIN) (4)

Nov 07, 2017
Qualification of Test 25 (Austin, Texas) as an Additional Wafer-Level Test Location.
Nov 06, 2017
Changes to Cypress Address Labels
Nov 06, 2017
Addendum to PIN 135258 - Qualification of JCET as an additional Test and Finish Location for Cypress Products
Oct 25, 2017
Notice of plan to transfer package manufacturing from Cypress Philippines to Jiangsu Changjiang Electronics Technology Co., Ltd. (JCET).