CY7C1470V33-200BZI | Cypress Semiconductor
CY7C1470V33-200BZI
Status: In Production
Datasheet
(pdf, 739.63 KB)
CY7C1470V33-200BZI
| Architecture | NoBL, Pipeline |
| Automotive Qualified | N |
| Burst Length (Words) | 0 |
| Density (Kb) | 73728 |
| Density (Mb) | 72 |
| Frequency (MHz) | 200 |
| Max. Operating Temp. (°C) | 85 |
| Max. Operating VCCQ (V) | 3.60 |
| Max. Operating Voltage (V) | 3.63 |
| Min. Operating Temp. (°C) | -40 |
| Min. Operating VCCQ (V) | 2.40 |
| Min. Operating Voltage (V) | 3.14 |
| Organization (X x Y) | 2Mb x 36 |
| Part Family | NoBL |
| Tape & Reel | N |
| Temp. Classification | Industrial |
Pricing & Inventory Availability
| 1-9 unit Price* | 10-24 unit Price* | 25-99 unit Price* | 100-249 unit Price* | 250-999 unit Price* | 1000+ unit Price* |
|---|---|---|---|---|---|
| $151.20 | $127.87 | $123.55 | $118.37 | $114.91 | $111.46 |
| Availability | Quantity | Ships In | Buy from Cypress | Buy from Distributors |
|---|---|---|---|---|
| Out of Stock | 0 | Please click here to check lead times | Contact Sales | Buy |
Packaging/Ordering
Package
No. of Pins
165
Package Dimensions
669 L x 1.4 H x 590 W (Mils)
Package Weight
629.20 (mgs)
Package Cross Section Drawing
Package Carrier
TRAY
Standard Pack Quantity
105
Minimum Order Quantity (MOQ)
105
Order Increment
105
Estimated Lead Time (days)
56
HTS Code
8542.32.0041
ECCN
(B.2.A.)
ECCN Suball
3A991
Quality and RoHS
Moisture Sensitivity Level (MSL)
3
Peak Reflow Temp. (°C)
220 (Cypress Reflow Profile)
RoHS Compliant
PB Free
N
Lead/Ball Finish
Sn/Pb
Marking
Package Material Declaration
Last Update: Aug 29, 2017
RoHS Analysis Certificates (CoA) for Direct Materials
Please click here
Technical Documents
Application Notes (3)
Product Change Notice (PCN) (8)
Oct 18, 2017
Qualification of JEDEC Shipping Tray for Sync and QDR SRAM products in 165 FBGA package
Oct 16, 2017
72Mb Synchronous SRAM CY7C14xx Family Revision B now released to full production
Oct 13, 2017
Change of assembly materials for all FBGA packages built in Advance Semiconductor Engineering (ASE) -Taiwan.
Oct 13, 2017
72M Synchronous SRAM design change to fix ZZ pin erratum and enhance internal test modes