CY7C1470V25-167BZC | Cypress Semiconductor

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CY7C1470V25-167BZC
Status: Obsolete

CY7C1470V25-167BZC

ArchitectureNoBL, Pipeline
Automotive QualifiedN
Burst Length (Words)0
Density (Kb)73728
Density (Mb)72
Frequency (MHz)167
Max. Operating Temp. (°C)70
Max. Operating VCCQ (V)2.60
Max. Operating Voltage (V)2.63
Min. Operating Temp. (°C)0
Min. Operating VCCQ (V)2.40
Min. Operating Voltage (V)2.38
Organization (X x Y)2Mb x 36
Tape & ReelN
Temp. ClassificationCommercial

Pricing & Inventory Availability

1-9 unit Price* 10-24 unit Price* 25-99 unit Price* 100-249 unit Price* 250-999 unit Price* 1000+ unit Price*
$168.00 $142.08 $137.28 $131.52 $127.68 $123.84
Availability Quantity Ships In Buy from Cypress Buy from Distributors
Out of Stock 0 Please click here to check lead times

Packaging/Ordering

Package
No. of Pins
165
Package Dimensions
669 L x 1.4 H x 590 W (Mils)
Package Weight
629.20 (mgs)
Package Cross Section Drawing
Package Carrier
TRAY
Standard Pack Quantity
105
Minimum Order Quantity (MOQ)
105
Order Increment
105
Estimated Lead Time (days)
42
HTS Code
8542.32.0041
ECCN
(B.2.A.)
ECCN Suball
3A991

Quality and RoHS

Moisture Sensitivity Level (MSL)
3
Peak Reflow Temp. (°C)
PB Free
N
Lead/Ball Finish
Sn/Pb

Package Material Declaration

Last Update: Aug 29, 2017

RoHS Analysis Certificates (CoA) for Direct Materials

Please click here

Technical Documents

Application Notes (3)

Product Change Notice (PCN) (8)

Oct 31, 2017
Q2, 2012 - Q4, 2013 Horizon Report
Oct 30, 2017
Q1, 2012 - Q2, 2013 Horizon Report
Oct 24, 2017
Qualification of Copper Wire Bonds for Ball Grid Array (BGA) Products
Oct 18, 2017
Qualification of JEDEC Shipping Tray for Sync and QDR SRAM products in 165 FBGA package
Oct 16, 2017
72Mb Synchronous SRAM CY7C14xx Family Revision B now released to full production
Oct 16, 2017
Shipping Label Upgrade
Oct 13, 2017
Change of assembly materials for all FBGA packages built in Advance Semiconductor Engineering (ASE) -Taiwan.
Oct 13, 2017
72M Synchronous SRAM design change to fix ZZ pin erratum and enhance internal test modes

Product Information Notice (PIN) (1)

Nov 06, 2017
Changes to Cypress Address Labels

Verilog (1)

Mar 17, 2015

IBIS (1)

Mar 15, 2011

VHDL (1)

Nov 13, 2008

BSDL (1)

Nov 13, 2008