Spansion Unveils Revolutionary MirrorBit(R) Eclipse(TM) Architecture, Combining MirrorBit NOR, ORNAND(TM) and Quad Flash Memory on a Single Die | Cypress Semiconductor
Spansion Unveils Revolutionary MirrorBit(R) Eclipse(TM) Architecture, Combining MirrorBit NOR, ORNAND(TM) and Quad Flash Memory on a Single Die
MirrorBit(R) Eclipse(TM) Architecture Will Enable Feature Phones and Multimedia Portable Devices with High Performance and Lower Costs; Reducing Handset OEM BOM Costs up to 30 Percent or More
SUNNYVALE, Calif., April 3, 2007 -- Spansion Inc. (Nasdaq: SPSN), the world's largest pure-play provider of Flash memory solutions, today unveiled its revolutionary MirrorBit(R) Eclipse(TM) architecture that combines MirrorBit NOR, ORNAND(TM) and Quad Flash memory on a single die. Compatible with existing chipsets, the MirrorBit Eclipse architecture can be adopted quickly to enable feature phones and multimedia portable devices with high performance and lower costs. Handset OEMs can save up to 30 percent or more on their handset memory subsystems bill of materials costs, while experiencing more flexibility in their designs.
"The MirrorBit Eclipse architecture is the result of a multi-year strategy to leverage a single technology, MirrorBit, to develop a broad range of solutions including NOR, ORNAND and Quad solutions to meet customers' requirements. Now with the MirrorBit Eclipse architecture, we will bring together all three solutions on a single die to deliver a powerful combination not previously possible in the industry," said Bertrand Cambou, president and CEO of Spansion Inc. "MirrorBit Eclipse architecture's ease-of-use and compatibility with existing platforms can enable handset OEMs to rapidly bring to market innovative feature phones at the same or lower costs to hit industry standard price points." Application Performance
With the increase of digital content on phones and multimedia portable devices such as pictures, music and video, the MirrorBit Eclipse architecture can enable improved performance such as fast application loading and boot times as well as fast image storage and retrieval.
Faster Time to Market and Lower Costs
Spansion strives to enable handset OEMs to reduce costs and enable faster programming time to produce phones more quickly. By taking advantage of the MirrorBit Eclipse architecture with its NOR interface and XIP (execute-in- place) approach, handset OEMs can reduce the amount of DRAM in the system. As a result of the MirrorBit NOR, ORNAND and Quad combination, performance improvements such as running code at blasting speeds and storing large amounts of multimedia content can be achieved on a single die. Additionally, the MirrorBit Eclipse architecture integrates a programmable microcontroller, which replaces the conventional state machine typically used in Flash memory and also supports built-in self test (BIST). MirrorBit technology's ability to efficiently integrate logic enables a production process that is more flexible and faster, enabling OEMs to get phones faster to market.
The company expects first silicon in Q3, and plans to sample 65nm MirrorBit Eclipse solutions built from 300mm wafers at its SP1 facility later this year. Based on 2-bit per cell MirrorBit technology, these solutions will have the ability to run code at the high speed of traditional NOR, while moving multimedia at very fast data rates. At 45nm, the solutions are planned to include both 2-bit per cell and 4-bit per cell storage, significantly increasing the density, and enabling the seamless combination of high- performance code storage with large blocks of multimedia storage capacity.
Spansion is a leading Flash memory solutions provider, dedicated to enabling, storing and protecting digital content in the wireless, automotive, networking and consumer electronics applications. Spansion, previously a joint venture of AMD and Fujitsu, is the largest company in the world dedicated exclusively to designing, developing, manufacturing, marketing and selling Flash memory solutions. For more information, visit http://www.spansion.com.
This release contains forward-looking statements that are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995, including statements regarding: (i) MirrorBit Eclipse architecture's ability: to be adopted quickly, to save OEMs on memory subsystem bill of materials cost; to enable OEMs to rapidly bring to market innovative feature phones at the same or lower costs; to enable improved performance such as fast application loading and boot times, fast image storage and retrieval and reduced energy burden from the memory subsystem; to reduce the amount of DRAM on OEM's systems; to store large amounts of multimedia content; and to enable OEMs to get phones faster to market; (ii) plans to sample 2-bit per cell 65nm MirrorBit Eclipse solutions on 300mm wafers at the company's SP1 facility in 2007 and plans to include 2-bit per cell and 4-bit per cell MirrorBit technology in its future 45nm MirrorBit Eclipse solutions, which may enable seamless combination of high-performance code storage with large blocks of multimedia storage capacity. Investors are cautioned that the forward-looking statements in this release involve risks and uncertainties that could cause actual results to differ materially from the company's current expectations. Risks that the company considers to be the important factors that could cause actual results to differ materially from those set forth in the forward- looking statements include the possibility that demand for the company's Flash memory products will be lower than currently expected; that the company will lose rights to key intellectual property arrangements and be subject to intellectual property infringement claims; that OEMs will increasingly choose NAND-based Flash memory products over NOR- and MirrorBit ORNAND architecture- based Flash memory products for their applications; that competitors may introduce new memory or other technologies that may make our Flash memory products uncompetitive or obsolete; that the company will fail to develop, or there will be a lack of customer acceptance of, MirrorBit NOR, MirrorBit ORNAND or MirrorBit Quad architecture-based Flash memory products; that the company will lose a significant customer; that the company will be adversely affected by its substantial indebtedness; that the company will not be able to raise sufficient capital to enable it to establish leading-edge capacity to meet product demand and maintain market share; that the company may not achieve facilities and capacity implementation schedules; that the company will not be able to reduce expenses; that the company will not successfully develop, introduce and commercialize new products and technologies or to accelerate our product development cycle; that the company will not be able to meet customer demand during cyclical industry or economic downturns; that the company may experience manufacturing constraints; that the company may be unable to diversify its customer base; that the company's investments in research and development may not lead to timely improvements in technology; that the company may not maintain manufacturing efficiency; the company's reliance on third-party manufacturers may harm it; that industry overcapacity may affect the company's prices and manufacturing capacity; that average selling prices may decline; and that the company's operations in foreign countries may be subject to economic and geopolitical risks. The company urges investors to review in detail the risks and uncertainties in the company's Securities and Exchange Commission filings, including but not limited to the company's Annual Report on Form 10-K for the fiscal year ended December 31, 2006. The company assumes no obligation to update any forward-looking statements or information included in this press release.
NOTE: Spansion(R), the Spansion Logo, MirrorBit(R), MirrorBit(R) Eclipse(TM), ORNAND(TM), HD-SIM(TM) and combinations thereof, are trademarks of Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners.