Wrong ADC Output - Possible Causes | Cypress Semiconductor
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Wrong ADC Output - Possible Causes
Even though there is a change in the input signal, the ADC output does not change. What could be the reason for this?
There are many reasons why an ADC would produce a Zero output or wrong output. Some possible reasons are listed below.
1. Check if the column clock to the ADC is within the limits specified in the ADC data sheet. If the column clock is greater than the specified limit, the ADC output would not be correct.
2. The ADC's column clock should be same as the Clock selection made in the user module's parameter. The output will be incorrect if the column clock and the Clock setting are different.
3. If the ADC's input is from another SC Block, then the ADC's clock phase parameter should be set to Swapped. An SC block has two phases of operation, the charge acquisition phase and charge transfer phase. During Phase-1, the output of an SC block is zero and the output is valid during Phase-2. When an SC Block output is connected to the ADC's input, the ADC would sample the input on Phase-1. But as the output of the previous SC block is zero during Phase-1, the output of the ADC would be alwasy zero. When the Clockphase is set to Swap, the ADC will sample the input on Phase-2 when the input would be valid.
4. If you are routing the output of a PGA to the ADC, check if the PGA has been started.
5. The Analog Power setting should have SC On / Ref x. If the power setting is SC Off / Ref x, all SC blocks will be turned off and the ADC will not work.