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Write Protect Settings | Cypress Semiconductor

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Write Protect Settings

Last Updated: September 19, 2011

What is the Write Protect feature for and how can I configure it?


The write protect is intended to prevent inadvertent corruption of the data stored in the EEPROM area while allowing I2C traffic to write to and read from the SRAM.

For example, assume I have an important spread spectrum profile information stored in the EE Block 5. This data is stored there even after powering down the device. While I write to the SRAM and perform my tests and make changes, I might want something that prevents altering my information in Block5 due to I2C traffic errors or other reasons.

Address 11H is the address of the register that allows configuring the write protect pin. The following table illustrates this content of this configuration address:


Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0









Bit 3 of 11H (the 4th bit) referred to as WPSrc determines where protect control signal should originate from. When WPSrc is set to low, the control comes from the active high write protect pin 17, provided the three least significant bits are 100. When WPSrc is set to high, the MemWP bit controls write protect.

Bit 4 of 11H (the 5th bit) referred to as MemWP is the internal setting that can be used to disable or enable writes to the EEPROM section. When WPSrc is set to 1, then a high on this bit disables writes to the EEPROM area and a low enables them.

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