Write Operation Timing of Asynchronous Dual-ports | Cypress Semiconductor
Support & Community
Write Operation Timing of Asynchronous Dual-ports
- When is the internal logic of an asynchronous dual-port latch the address during a write cycle?
- Is the address latched when CE# transitions to low?
- Do write operations begin when R/W# transitions to low or when CE# and R/W# both transition to low?
The moment that the internal logic of the asynchronous dual-port latches the address is dependent on whether the write operation is controlled by either the R/W# signal or the CE# signal. It will depend on which one was asserted first. The waveforms for both of these cases are shown on page 12 of the CY7C024AV datasheet.
In the case of the R/W# controlled write operation (the top waveform on page 12), the CE# signal is asserted low before the R/W# signal. The address is then latched when the R/W# signal transitions low.
In the case of the CE# controlled write operation (the bottom waveform on page 12), the R/W# signal is asserted low before the CE# signal. The address is then latched when the CE# signal transitions low.