Why tS > tSPT for Ultra 37000 CPLDs | Cypress Semiconductor
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Why tS > tSPT for Ultra 37000 CPLDs
Why is tS > tSPT?
Setup is the amount of time before the clock edge when the data must be static. Consider the two input paths in two arbitrary devices with made-up timing numbers -- for the "tSPT" device, the data delay is 4ns and the clock delay is 4ns. For the "tS" device, the data delay is 4ns and the clock delay is 2ns, since the clock tree is faster than the datapath. Now assume that both devices have the same register internally, and this register has a "micro-tS" of 0ns. That is, the setup-time referenced to the internal inputs of the register (not the external pins) is 0ns. When you take into account the delays for the signals from the pins, you end up with a ts of 0ns for the tspt case, and 2ns for the ts case. The skew between the two clock and data signals due to the clock tree is responsible. Since the clock gets to the register faster for ts, you've lengthened the setup window. The opposite, of course, will happen for hold time. Further, note that "true" setup + hold externally referenced is a constant determined by the register. The reason it is not reported as a constant in the datasheet is due to the fact that a negative hold time tends to confuse people. Therefore, it is reported as 0 to prevent confusion.
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