Vih and Vil values when LDO enabled in CY8C20X66 | Cypress Semiconductor
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Vih and Vil values when LDO enabled in CY8C20X66
Last Updated: March 13, 2012
If LDO on port 1 of CY8C20X66 is enabled for 1.8V, output signal levels(Voh, Vol) will be as per 1.8V Vdd, but what will be the input signal voltage specs(Vil, Vih)?
To avoid voltage compatibility issues, there is a provision to reduce threshold voltage of input buffers. This can be done by setting bit P1_LOW_THRS (bit 3) in register IO_CFG1.
By setting this bit, Vil and Vih will be 1.366V and 1.476V respectively.