Verilog statement with the tristate value Z generates an error in PSoC Creator | Cypress Semiconductor
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Verilog statement with the tristate value Z generates an error in PSoC Creator
How to assign High Z state to a pin in Verilog?
Any Verilog statement that includes the tristate value Z will generate an error when the design is built.
assign bidi = (state == 2'd0) ? 1'b0 : 1'bz;
The solution is to replace the statement with a cy_bufoe component as follows:
wire oe = (state == 2'd0);
cy_bufoe buf_bidi (
.x(1'b0), // (input) Value to send out
.oe(oe), // (input) Output Enable
.y(bidi), // (inout) Connect to the actual bidirectional pin
.yfb()); // (ouptut) Value on the pin brought back in