Variation of Parasitic Capacitance (CP) Between Segments in a Slider Design Using Dual IDAC Mode – KBA91404 | Cypress Semiconductor
Support & Community
Variation of Parasitic Capacitance (CP) Between Segments in a Slider Design Using Dual IDAC Mode – KBA91404
How much parasitic capacitance (CP) can vary from one segment to another segment in a slider design using dual IDAC mode?
A slider has many segments that are separately scanned and the centroid algorithm is applied finally on the signal values of all the segments to calculate the centroid position. The CapSense® algorithm implements a specific tuning method for slider to avoid nonlinearity in the centroid that could occur due to the difference of CP in the segments. However, the following layout conditions need to be met in order for the slider to work.
- CP of any segment should always be within the supported range of 5-45 pF. To meet this condition, ensure that the layout best practices provided in the CY8CMBR3xxx CapSense design guide are followed
CP of other segments should be greater than 75% of the CP of the segment with the maximum value in that slider. For example, if the CP of the segment with the maximum value is 30 pF, the Cp of other segments should be greater than 22.5 pF. The PSoC device families that support dual IDAC mode are CapSense MBR3, CY8C20xx7/S, and PSoC 4.
Implement the following layout design rules to meet this condition:
- Design the shape of all segments to be as uniform as possible.
- Keep the length and the width of the traces connecting the segments to the CapSense controller the same for all segments.
- Maintain the same air gap between the sensor or traces to ground plane or hatch.