Using Parity SRAMs in Non Parity Applications | Cypress Semiconductor
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Using Parity SRAMs in Non Parity Applications
How to use Parity SRAMs in Non Parity Applications
Cypress offers parity SRAMs (x18 and x36) that allow parity checking to be done in x16, x32 or wider systems. The parity
check must be performed external to the SRAMs. The parity bits act identically to nonparity or data bits. No special circuitry
is added or associated with the parity bits.
It is recommended that the parity pins not be left floating if unused. Floating pins can increase the power dissipation of
the device during Write cycles.
Figures 1 and 2 show the recommended connection of the parity pins to GND. Note that these pins could be connected to VDD (3.3V) instead. Although a 1-KΩ resistor is shown in the diagram, other values can be used. The recommended range
of resistance is 1 KΩ to 10 KΩ. Choosing a resistor closer to 1-KΩ provides a lower impedance to the power plane and makes the pin less susceptible to noise. The 1-KΩ resistor is the preferred value because the power difference between 1 KΩ and 10 KΩ only occurs until the entire memory array is written. The resistors dissipate power if the parity bit read out is HIGH and the resistor is connected to GND. As the memory array gets written with data (GND), this power dissipation goes away.
A separate resistor is required for each parity pin (DQP). The SRAM powers up with the memory array set in a random state. If all parity pins are connected to a single resistor, bus contention may initially occur during READ cycles until all of
the address locations are written. Separate resistors alleviate this problem.