Using inout pins in Verilog during Custom Component creation in PSoC Creator | Cypress Semiconductor
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Using inout pins in Verilog during Custom Component creation in PSoC Creator
How to use inout pins in Verilog during Custom Component creation in PSoC Creator
There are two different ways to handle inout pins depending on whether Tristate logic should be included in design or not.
1) When Tristate logic is not included: In such situations an inout pin can be used in verilog. A bidirectional pin should be connected to the inout pin. The preferred drive mode would be Open Drain Low/High. Depending on the drive mode the pin should be pulled up/down. Read/Write operations can be performed on the pin in the normal manner.
2) When Tristate Logic needs to be included: A convenient way of including Tristate logic is by using the “Bufoe” component. The Bufoe component is available in PSoC Creator Component catalog under the section Digital -> Logic -> Bufoe.
In this case the verilog module should have separate input and output pins instead of inout pin and these should be connected to the yfb and x pins of the Bufoe component. The output of the Bufoe component ‘y’ should be brought out as the inout pin of the final component.
A sample schematic of using the Bufoe component to build a bidirectional D Flip Flop is as follows.
The Bufoe component can also be used inside a verilog module by instantiating the cy_bufoe module. The tri-state output of this module, y, must then be connected to an inout port on the Verilog module. That port can then be connected directly to a bidirectional pin on the device. The feedback signal of the cy_bufoe, yfb, can be used to implement a fully bidirectional interface or can be left floating to implement just a tri-state output. The cy_bufoe instantiation is as follows.
cy_bufoe buf_bidi (
.x(), // (input) Value to send out
.oe(), // (input) Output Enable
.y(), // (inout) Connect to the bidirectional pin
.yfb() // (ouptut) Value on the pin brought back in