Usage of CPUCS register to reset the 8051 core in FX1/FX2/FX2LP | Cypress Semiconductor
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Usage of CPUCS register to reset the 8051 core in FX1/FX2/FX2LP
In FX1/FX2/FX2LP, can the firmware reset the 8051 core by setting the bit 0 of CPUCS register?
No, the bit 0 of CPUCS register is a Read-Only bit and firmware cannot manipulate this bit to put the 8051 to a reset. The USB host writes "1" to this bit to reset the 8051, and "0" to run the 8051. Only the USB host can write to this bit (via the 0xA0 firmware load command).
For soft reset, refer the knowledge base article in the link Soft Reset in EZ-USB(AN21xx/FX/FX1/FX2/FX2LP)