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Upgrading CapSense projects to PSoC Designer5.0 SP5.0 or higher | Cypress Semiconductor

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Upgrading CapSense projects to PSoC Designer5.0 SP5.0 or higher

Last Updated: June 19, 2011
Question: 

When I upgrade PSoC Designer 5.0 to SP5.0 or higher, CapSense (In devices CY8C20x34, CY8C20x46, or CY8C20x66) does not work properly. What may be the reason?

Answer: 

There was a bug in PD5.0 SP4 & SP4.5. Upon reopening and generating/building a CY8C20x34, CY8C20x46, or CY8C20x66 project, the generated code disables any connections to the Analog Mux Bus shown in the chip level view.

If you had made any manual connections of pins to the Analog mux bus in the chip level view of the project (in SP4 or SP4.5), then these connections were not implemented in the generated code. Hence, the functionality of CSD user module was not affected.

When you upgraded to SP5.0 or higher version of PD5.0 where the bug is fixed, it actually implemented the manual connections of pins to the Analog mux bus (by setting MUX_CRx registers properly), which you had done in chip level view before. These undesired connections caused the improper functionality of CSD user module in SP5.0 (or higher).

To fix this, go to the chip level view of project & break the connections of the pins to Analog mux bus which you had done manually. If your project has CSD & any other user module which needs Analog mux bus for its operation (such as ADCINC user module), then in firmware of the project write the code in such a way that Analog mux bus is used by them in time division multiplexed form. Example: For ADCINC user module, If you want to convert the analog voltage level on port pin P0[0] to digital form, then before starting the A-D conversion, connect P0[0] pin to the Analog mux bus by setting bit-0 of MUX_CR0 register. After the conversion is completed, break this connection by clearing the bit-0 of MUX_CR0 & then assert the CSD scanning process.

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