Tying two (unidirectional) FIFO outputs together | Cypress Semiconductor
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Tying two (unidirectional) FIFO outputs together
Can I safely tie two outputs together in case of depth cascading? or How should I set up my system to switch from one data bus to another when using two FIFOs? or Can I use the output enables (OE#) to switch from one bus to another if they are tied together?
To safely connect two outputs together (especially in the case of depth expansion when data lines are shared), it is very important to use each FIFO's Output Enables carefully to ensure that there is no contention. Assuming that FIFO1 is read before FIFO2, there will be data contention unless OE# of FIFO1 must be de-asserted (HIGH) before OE# of FIFO2 is asserted. That way the data bus of FIFO1 is forced to a High-Z state before FIFO2 data is driven. If both FIFOs are sharing a single RCLK, OE1# will have to be switched some time after tA, but within the cycle of RCLK in order to have no cycles between reads (assuming OE2# switches at the following rising edge of RCLK).