Troubleshooting Guide for nvSRAM and FRAM – KBA94279 | Cypress Semiconductor
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Troubleshooting Guide for nvSRAM and FRAM – KBA94279
This guide addresses common issues that occur with FRAM- and NVSRAM-based systems. You can troubleshoot the majority of your nvSRAM and FRAM issues using the information provided in this guide.
When you use the nvSRAM real-time clock (RTC) for the first time, or migrate from an older nvSRAM RTC device to a newer one, the nvSRAM RTC functions may not work as expected. This ususally happens when the RTC design does not follow the datasheet recommendations.
If you are having trouble with the nvSRAM RTC, please check the following:
- The oscillator enable bit D7 (OSCEN) of the calibration/control register 0x08 is cleared to zero. This bit is used to enable or disable the oscillator circuit within the device.
- The load capacitances (C1 and C2) on the crystal pins (XOUT and XIN) are connected per the recommended values provided in the device datasheet.
- The selected RTC crystal load capacitance (CL) is in accordance with the recommended load in the datasheet. A typical nvSRAM RTC requires 12.5-pF load capacitance.
- A few of Cypress’s older nvSRAM RTC parts require you to connect a feedback resisitor (RF) of value 10 MΩ across the XIN and XOUT pins of the nvSRAM. The feedback resistor (RF) is integrated into all the new nvSRAM RTC devices. The datasheets of these parts will show only the crystal, C1, and C2 as the recommended components at the XOUT and XIN pins. Therefore, the feedback resisitor (RF) must be set to “do not install” or “do not connect” if migrating from an older version of nvSRAM to a newer version on the same (old) socket.
- Follow the RTC layout design guidelines and best practices explained in AN61546 - Non Volatile Static Random Access Memory (nvSRAM) Real Time Clock (RTC) Design Guidelines and Best Practices to achieve the desired clock accuracy in the system.
- Do not measure the RTC output clock by probing directly on either the XIN or XOUT pin of the device because the probes load the crystal pin and thus impact the RTC clock accuracy.
- To measure the RTC clock frequency, measure the digital output clock on the INT pin by setting the calibration bit D2 to ‘1’ (CAL = 1) in the flags register 0x00. Once the CAL bit is set to ‘1’, the INT pin generates a 512-Hz square wave output when the 32768-Hz crystal is oscillating with zero-ppm error. Otherwise, depending upon the accuracy of the crystal, the square wave output will vary from its nominal frequency of 512 Hz . The RTC clock error can be corrected by using on-chip software calibration. Application note AN53313 - Real Time Clock Calibration in Cypress nvSRAM gives the details on software calibration. Note that software calibration does not correct the clock at the INT pin.
- It is a best practice to install the battery on the VRTCbat pin while VCC is applied. When the battery is installed before applying the VCC, the internal RTC circuit remains in an unknown state and may consume more than the rated backup current (IBAK). This is a critical consideration only for the battery backup.
- When setting a new base time, execute a software store to save the new time to the nonvolatile time registers. The software store should be inititated tRTCP time after the RTC write bit D1 is cleared (W = 0) in the flags register 0x00.
- In general, for any issues with the RTC, take a dump of all 16 RTC registers by following the steps given below. Checking the register data dump shows you the staus of the timekeeping registers and other status registers mentioned above.
- Power up the device (wait for two minutes).
- Read all RTC registries.
- Power down the device.
- Wait three to four minutes.
- Power up the device. Read all the RTC registers.
- If you are seeing corrupted data on power up (typically at the 0x0000 address), connect a pull-up resistor on /WE and check if this solves the problem.
More details are given in the KB article, Pull up resistor on WE# control line of nvSRAM.
- If you are seeing data corruption on power up even after connecting a pull up on /WE, ensure that the controller/FPGA is configured to tristate its pins during the boot-up phase.
More details are given in the KB article, Corruption in a particular location of nvSRAM even though WE# is pulled up to Vcc.
- If Autostore is not happening at all in the nvSRAM device, do the following test to confirm if Autostore has failed:
Power up -> Write AA in location 00 -> Read to confirm -> power down -> power up -> read location 00 -> Is it AA? -> If yes, write 55 in location 00 -> Read to confirm -> power down -> power up -> Read location 00 -> Is it 55? If it is not 55, is it AA?
If the data is AA, autostore has failed. If it is 55, Autostore happened. If the data is something else, Autostore has happened, but some corruption happened after powering up the device.
- If it is confirmed that Autostore failed, check the VCAP value on the board. It has to be in the range given in the respective device datasheet.
- Some of the devices have an Autostore disable feature. By default, Autostore is enabled in all the devices. To ensure that Autostore is enabled, use the following method:
- Send the Autostore enable sequence.
- Issue a software store.
- Power cycle, read the data, and verify Autostore has happened.
NVSRAM Block Protect
- Some of the NVSRAMs have a Block Protection feature which protects one quarter, one half, or the full memory array. By default, Block Protection is disabled. If you are not able to write to any of the memory locations, say the upper half, read the status register bits BP0 and BP1 to make sure the Block Protection feature was not set by mistake.
FRAM Access issues
- If you are having trouble accessing the FRAM device (read/write), verify that the VDD ramp rates (tVR and tVF) are greater than the minimum values given in the respective datasheet.
- If your VDD ramp rates are correct and the device is still not responding, check if you are waiting for tPU time from VDD for the first access to the FRAM. In the case of processor companions, a reset will be active for tRPU time after VDD rises above VTP.