Troubleshooting Guide for CapSense® MBR3 Designs - KBA210900 | Cypress Semiconductor
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Troubleshooting Guide for CapSense® MBR3 Designs - KBA210900
This guide addresses common issues that can occur in CapSense MBR3-based designs. If you are new to MBR3 and CapSense, then get started with AN64846 - Getting Started with CapSense®. More related references are provided in the Appendix section of this document.
- Unable to Configure MBR3 with Host Controller
- Sensors Do Not Respond when Touched.
- Touches Reported when No Touch Present.
- Frequent I2C NACK when Communicating with MBR3.
- Unable to Dynamically Change PWM Duty Cycle.
- High Current Consumption of MBR3.
- How to Reset the MBR3 Configuration to Factory Defaults.
- Controlling GPO from both Host Controller and CapSense Sensors.
If the host controller is not able to configure MBR3, the problem can be because of the following:
1.1 I2C Communication
- Ensure the I2C lines are pulled up to VDD with a resistance of 2.2 kW-6.5 kW typically.
- Ensure that the AXRESn pin of the chip is not pulled LOW. See MBR3xxx_Datasheet to know the AXRESn pin number for the corresponding device.
- The default I2C slave address of MBR3 is 0x37 (7-bit addressing). The Master should use this address unless it is changed.
- MBR3 is designed for low power consumption; therefore, it undergoes a wake-sleep sequence periodically. When MBR3 is in sleep, if there is any I2C transaction, MBR3 will NACK. The host should retry within 340 ms with a new transaction. The first transaction acts as the wake-up source for MBR3 to wake up from sleep mode. Therefore, after the first transaction, the host should reinitiate the transaction within 340 ms after which MBR3 will again go to sleep.
1.2 Configuration Data
- The 128 byte data to be written to MBR3 through I2C can be fetched from the .IIC file generated from your EzClick project. Figure 1 shows the IIC file opened in the Bridge Control Panel software (Installed in the system along with PSoC Programmer) and highlights the 128-byte data. This data can be used in your host control program to configure the MBR3 device.
Figure 1. Example IIC File with the 128-Byte Hex Data Highlighted
Note: If the configuration data is changed after fetching from the IIC file, the CRC will no longer be valid and MBR3 configuration will not be successful. The ‘Save to flash’ command (CMD=0x02 in the CTRL_CMD register) will not be executed successfully; this will be returned as an error in the CTRL_CMD_STATUS register. Therefore, every time the configuration is changed, the new CRC should be calculated by the host or retrieved from the new IIC file generated by the EzClick software. The last two bytes of configuration data is the CRC value.
1.3 Configuration Sequence
Follow the steps detailed in Section 5.2.3 in CY8CMBR3xxx CapSense® Design Guide for the configuration sequence. See Section 5.2.3 for detailed steps on configuring through host APIs.
If there are issues with MBR3 sensors not responding, check the following:
- Power On Self-test: Ensure that the sensor hardware condition is not faulty by running system diagnostics Power On Self-Test. Detailed information is available in CY8CMBR3xxx CapSense® Design Guide in Section 184.108.40.206.
- Sensitivity and Threshold Settings: The Sensitivity should be set such that the SNR upon a finger touch is 5:1. Follow the tuning procedure in Section 6 of CY8CMBR3xxx CapSense® Design Guide.
- High Parasitic Capacitance (Cp): The parasitic capacitance of sensors directly affects the sensitivity. A higher parasitic capacitance gives reduced signal in response to a finger touch when compared to sensors with a lower Cp. If Cp is above 45 pF, the sensor would be disabled. Cp can be read through I2C from the register DEBUG_CP (0xDD) as well as from the EzClick software in the CapSense Output window as shown in Figure 2. Ensure that your design follows the proper layout guidelines provided in the CY8CMBR3xxx CapSense® Design toolbox to keep Cp in the desired range.
Figure 2. Reading Cp from EzClick
- Overlay thickness: A thicker overlay reduces the signal. The maximum recommended overlay thickness for acrylic is 5 mm and for glass is 15 mm. An overlay with a higher dielectric constant provides a better signal. Dielectric constants for a few overlay materials are given in AN64846 - Getting Started with CapSense®. Ensure that there are no airgaps when pasting the overlay on the PCB. Air gaps significantly degrade the sensitivity.
- Guard Sensor: If a guard sensor is used in your design, and if the guard sensor is active, all sensors are disabled. To check whether a guard sensor is getting activated when other sensors are touched, read the status of the guard sensor when other buttons are touched in the EzClick software or by reading the BUTTON_STAT register. Ensure that the sensitivity of the guard sensor is kept at the lowest.
- Neighboring Button Triggers when a Button is Touched: This issue can arise either due to the higher sensitivity of neighboring buttons or due to an improper layout design. Check if the neighboring buttons are oversensitive. Oversensitive means a sensor reporting touch outside of the active area of touch. Reducing the sensitivity and increasing thresholds can be tried to reduce the oversensitivity of the buttons. In the layout, ensure that adjacent sensor traces are not routed below the sensor and the sensors are not closely spaced. For closely spaced buttons, the Flanking Sensor Suppression (FSS) feature can be used to prevent simultaneous detection of two buttons. Refer to FSS in Section 220.127.116.11 of CY8CMBR3xxx CapSense® Design Guide.
- Poor SNR and Cross Talk: High noise in the CapSense system can be due to an improper layout and surrounding environment conditions. Digital nets such as I2C and GPOs should not be routed in parallel with sensor lines to avoid cross talks. Proper grounding should be given between VDD nets and sensor traces as noise in Vdd can couple to sensors. Follow the layout guidelines presented in the CY8CMBR3xxx CapSense® Design toolbox. The EMC feature can be enabled if the system is exposed to electromagnetic interference from surrounding ICs or antennas.
This is an expected behavior. As explained earlier, MBR3 has low-power modes and therefore goes to sleep periodically. If an I2C transaction is NACKed, reinitiate another transaction within 340 ms. See I2C Communication Guidelines given in MBR3xxx_Datasheet.
When a new PWM duty cycle is written into MBR3, the new duty cycle output does not take immediate effect. You should issue the ‘save to flash’ command followed by a software reset for the new value to come into effect. For details on the save to flash command and the software reset, see the CTRL_CMD register in MBR3xxx_RegisterTRM.
This can be due to improper GPO terminations. Ensure that unused GPOs are connected per the recommendations given in Table 1 of MBR3xxx_Datasheet. Other factors affecting power are given in Section 7.2 of CY8CMBR3xxx CapSense® Design Guide.
The device internally has the ability to restore factory defaults; this happens only when the saved configuration in the nonvolatile memory is invalid (due to incorrect CRC). This can occur only due to rare situations of power-off when the device is saving a user configuration into the nonvolatile memory (by the CTRL_CMD). Therefore, there is no direct option for you to reset the device to factory default configuration. However, you can write a suitable API in your I2C host controller to write the factory default values to the device registers. These values are tabulated in Section 1.4, “Factory Default Values” of the MBR3xxx_Datasheet .After this, use the 0x02 option in the ‘CTRL_CMD’ register to save these values into the nonvolatile memory and reset the device for the values to take effect.
A GPO can be controlled through the host or by CapSense sensors. If the GPOs are controlled by CapSense sensors, the corresponding GPO(GPx) is driven when the button is touched.
In host control, the host controller can control the GPOs independent of the CapSense button status by writing into the GPO_OUTPUT_STATE register. Only one of these methods of GPO control is available at a time. Host Control can be enabled or disabled in the Global Configuration section of the EzClick project as well as by writing into Bit 0 of the GPO_CFG register.
The following links provide several important CapSense MBR3 documents: