Tracking skew - CY7B994V | Cypress Semiconductor
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Tracking skew - CY7B994V
What is the tracking skew of CY7B994V?
Usually tracking skew or tracking jitter is not specified in most of RoboClock data sheets. However, RoboClock datasheets have a Total Timing Budget (TTB) specification in them. The TTB for our
CY7B994V-2 device is 500 ps maximum and for our
CY7B994v-5 device is 700 ps maximum. TTB tries to specify the worst-case timing you will ever see from the chip. Please find attached below a slide showing that TTB includes skew plus all necessary jitter to give the total maximum uncertainty you should ever see. For PLL devices, we usually specify the cycle-to-cycle jitter only as cycle-to-cycle jitter is important for the system using PLLs in serials. If the cycle-to-cycle jitter is too high, it may cause downstream PLL lose lock or high tracking skew. It should be noted that PLLs are normally capable of tracking long-term jitter. PLLs, by design, are incapable of tracking cycle-to-cycle jitter, because the PLL response time is typically slow. When the modulation occurs at a rate and level that is too difficult for a PLL to track, the PLL may give a best-effort tracking which we refer to as tracking skew.