Timing specification between SLOE and SLRD in EZ-USB FX2 | Cypress Semiconductor
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Timing specification between SLOE and SLRD in EZ-USB FX2
There are no timing restrictions between SLRD and SLOE specified in the FX2 datasheet. Can you please clarify what is the timing requirement between SLOE and SLRD for FIFO read in synchronous and asynchronous mode?
The SLOE and SLRD are two seperate input signals that do not have any related timing specification. Based on the application needs these two input signals may be tied together.
From the timing diagrams in the datasheet, you will note that the tOEN (SLOE Turn-on to FIFO Data Valid) is always less than tSRD (setup time for SLRD) for a synchronous read. For asynchronous read, tOEN (SLOE Turn-on to FIFO Data Valid) is also always less than tXFD (SLRD to FIFO Data Output Propagation Delay). So as long SLOE meets the specified tOEN there should be no problems. As long as SLOE is in an asserted state when SLRD is asserted, it should be fine and the two signals can be tied together for certain applications where the external master has only one output control signal for reading from the FX2 FIFO.