Time Violation Warning Messages Static Timing Analysis (STA) for a SPI-Based PSoC® Creator™ Project - KBA94528 | Cypress Semiconductor
Support & Community
Time Violation Warning Messages Static Timing Analysis (STA) for a SPI-Based PSoC® Creator™ Project - KBA94528
How do I handle STA warnings that arise for a SPI-based PSoC® Creator™ project?
The following is the format of warning messages that you might get:
sta.M0019: time_violation_timing.html: Warning-1367: Hold time violation found in a path from clock ( CyBUS_CLK ) to clock ( Pin_6(0)/fb ). (File=C:\Users\gore\Documents\PSoC Creator\ndkfgjkl\ndkfgjkl.cydsn\ndkfgjkl_timing.html)
You might see these warning messages because you may have selected the "Double-Sync" option for SPI Master (SPIM) and SPI Slave (SPIS) input pins as shown in Figure 1. It is recommended to select the option “Transparent”.
Figure 1. Set Sync Mode to "Transparent"
Figure 2. Sync Mode Setting for Input Pins