Synchronous FIFO Flag Update Cycle | Cypress Semiconductor
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Synchronous FIFO Flag Update Cycle
- What is the Flag Update Cycle?
- Must the FIFO be read to update the empty flag?
- Must the FIFO be written to for the full flag to be updated?
A flag update cycle (otherwise known as boundary latency cycle) refers to
the clock cycle which updates the synchronous flags at a boundary. The
empty flag gets updated by the read clock (RCLK) and the full flag gets
updated by the write clock (WCLK).
You don't have to read data from the FIFO to update /EF as long as you
keep the RCLK running at all times. The empty flag (/EF) will get updated
when the first piece of data is written into the FIFO regardless of whether
you're reading from the FIFO. When starting with an empty FIFO it essentially
takes two read clocks to read the first word from the device. The first read
clock rising edge updates the Empty Flag (assuming a write has been
performed). This update cycle occurs whether the read is enabled or not.
The second read clock rising edge (enabled) will read the first word from
the device. Without asserting the read enable (REN) a read will not be
The same applies to the full flag (/FF). Keeping the WCLK running at all
times will make sure the /FF is updated right away. When the device is
full, a write clock is needed to update the full flag (FF). In this case it takes
two write cycles to write into a device which just became not full.
This type of flag operation is necessary to ensure that the empty and full
flags will be valid and usable for a minimum of one clock cycle. This
architecture eliminates short flag pulses characteristic of an asynchronous
FIFO. This concept is the same for devices that have dual-function pins.
EF#/OR and AE# should be synchronized to CLKB, whereas FF#/IR and
AF# are synchronized to CLKA.