Synchronous FIFO Clocks | Cypress Semiconductors
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Synchronous FIFO Clocks
- Are there any requirements for clock duty cycles?
- Do the clocks have to have 50 percent duty cycles?
- What are the requirements for the clock driving sync FIFOs?
The clocks driving a synchronous FIFO do not have to be of 50% duty cycle. As long as tCLKH (clock high) and tCLKL (clock low) minimums are met, the FIFO will function correctly. In addition a few devices specify that all inputs meet a certain minimum rise and fall time. Since the clocks are input signals, it is necessary to meet these requirements. For example, in most low voltage devices (i.e. CY7C43664AV), there is a minimum rise and fall time of 3 ns for all input pulses. This 3 ns is measured from 10% of Vin to 90% of Vin. So if Vin = 3.0V, the rise time is the time it takes to go from 0.3V to 2.7V. The fall time is then the time it takes the input to go from 2.7V to 0.3V. Otherwise, the clocks must simply meet the input standards described by the datasheet.