You are here

Static Timing Analysis in PSoC Creator | Cypress Semiconductor

Support & Community

Static Timing Analysis in PSoC Creator

Last Updated: June 22, 2011

Question: What does Static Timing Analysis mean in PSoC Creator?


Static Timing Analysis engine automatically analyses the following Digital timing aspects in the PSoC3 device:

  • Propagation Delay: Purely combinational delay from an input to an output.
  • Clock-to-output Delay: Delay from a clock source through a register to an output.
  • Setup Time: Difference between the delay from a clock source to a register and an input to a register.
  • Register-to-register Delay: Delay from the output of a register to the input of a register. The static timing analyzer will compute the maximum frequency if both registers have the same clock.

Static timing analysis identifies delays in a design’s digital logic and computes the maximum frequency for each clock. The static timing analysis report shows the critical paths in the design that limit the clock frequency. If the actual clock frequency exceeds the calculated maximum frequency, the report indicates a timing violation in the design.

Provide feedback on this article

Browse KB By Product

Browse KB by Type