Speed Up Slave FIFO Transfer (FX2) | Cypress Semiconductor
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Speed Up Slave FIFO Transfer (FX2)
Can I speed up a Slave FIFO transfer by asserting SLWR for consecutive IFCLK cycles, assuming the the programmable flag is continuously monitored?
In asynchronous mode (IFCONFIG.3 = 1), SLRD and SLWR are read and write strobes and these need to be asserted for each data byte/word transfer. Of course the interface needs to meet the timing as shown section 9.7 and 9.9 in the datasheet. This transfer can be sped up if the interface is set in synchronous mode. The rate is much slower in asynchronous mode, as the SLWR and SLRD need to be pulsed for each transfer. In synchronous mode (IFCONFIG.3 = 0), SLRD and SLWR are enables for the IFCLK clock pin and should be left asserted until all the transfer is completed. In this mode, data on the FD bus is written to the FIFO (and the FIFO pointer is incremented) on each rising edge of IFCLK while SLWR is asserted.
FX2 Technical Reference Manual
EZ-USB FX2 Datasheet