SLRD/SLWR Pins During GPIF Mode of FX2LP | Cypress Semiconductor
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SLRD/SLWR Pins During GPIF Mode of FX2LP
During GPIF burst transaction, is the GPIF in control of the SLWR, SLOE signals internally? Do I need to tie the appropriate CTLx output signals to these signals?
The SLWR, SLRD, SLOE pins are only active when FX2LP is configured in Slave FIFO mode. These pins assume a different functionalities when FX2LP is not operating in Slave FIFO mode. For example, when configured in GPIF mode, the SLRD and SLWR lines are replaced with RDY0 and RDY1 lines respectively.