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Slightly High FX2 Drive Levels on Test J or Test K | Cypress Semiconductor

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Slightly High FX2 Drive Levels on Test J or Test K

Last Updated: December 31, 2011

When performing the Test J or Test K test mode commands, the D+ and D- lines are measured to be 448 mV when asserted and 11 to 12 mV when de-asserted. I have a captive (tethered) cable design and measurements were made at a termination fixture at the end of the cable. When measuring the D+ and D- traces on the board itself, the voltage levels pass in the high state, but barely (438mV and 2-4mV). Why is the drive level so high?
Does the USB-IF allow the Test J/K voltage levels to be measured from the board directly, or must they be measured at the far end of the captive cable?


At the USB-IF compliance workshops, the measurements are always done at the test fixture, never at the chip. The problem may be the termination of the cable. The shield and ground wires should be properly connected to the board. Make sure that the engineering unit and the flexing of the cable hasn't caused the cable to break many of the shield strands. If this occurs, the resistance of the cable will be high.

Also ensure that the USB 2.0 cables/connectors are certified compliant. The USB-IF website ( has a list of certified compliant cables and connectors.

You may also want to check at the chip and see if the offset is lower. Then try a short on the shield to ground to see if the offset changes. Some designs implement a resistor/capacitor network between the shield and the ground to help with ESD and EMI in noisy environments. However, several designs have had the ground and shield shorted without any problems.

If the short on the shield to ground reduces the offset, most likely you have a current flow (small amount), which is giving the offset. The system you are using should have one point where they are connected together. A normal system design would have a single point which connects these two points and the host computer should have this setup.

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