Slave FIFO Address Lines for the CY7C68013 (FX2) | Cypress Semiconductor
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Slave FIFO Address Lines for the CY7C68013 (FX2)
Figures 9-11 and 12 in the Technical Reference Manual present a small state machine on how to perform FIFO writes in asynchronous mode. Is it necessary to pass all the states in the state machine described in this section? Can I set FIFOADDR lines before one clock, perform a write cycle on the next clock, and subsequently change FIDOADDR lines in order to perform a write to a different endpoint?
Section 9.2.7 of the Technical Reference Manual provides a step-by-step sequence that the master requires to write to the SLAVE FIFO. Following this sequence will ensure that you are meeting the timing (hold and setup) as stated in section 9.9 of the EZ-USB FX2 Datasheet.
You may change the FIFOADDR lines anytime to address a different FIFO. However, make sure that you abide by the FIFOADDR lines hold time with respect to the activating edge of the SLWR as stated in 9.15 of the datasheet. As long as you meet the setup timings of SLWR, FIFOADDR and FD, as per the datasheet you should be fine.