Sigma Delta ADC and Decimator Bit Discrepancy | Cypress Semiconductor
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Sigma Delta ADC and Decimator Bit Discrepancy
Question: Why is the Sigma Delta ADC only 13-bit when the decimator is 16 bits?
Response: A Sigma Delta ADC can only utilize 14-bits of the decimators 16-bit math. The remaining 2-bits are noise. This condition is only true when using the DelSig in the CY8C29x66 and when using both the double modulator and 8-bit incremental. You can also achieve 14-bits by using a DesSig11 and left-justifying the "data position" in the user module parameters. Refer Application note AN2239 - ADC Selection