Settling time | Cypress Semiconductor
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Last Updated: January 16, 2012
What is settling time?
How to set the settling time for a capsense project?
Settling time is the amount of time given by the CSA user module for the voltage on Cmod to reach Vstart. This is accomplished by connecting a current source to an equivalent resistor created by a switch capacitor network around the parasitic capacitance of the button. There is an external capacitor used in CSA, often referred to as Cmod, which creates an RC filter with the equivalent resistor. The proper settling time(minimum) is five time constants of this RC network.
So settling time,
where Cp is the parasitic capacitance value,
Fcsa is the clock frequency given to the csa module
So the settling time is inversely proportional to the parasitic capacitance. For lower Cp the system requires higher settling times. Conversely,for larger Cmods, the system also requires higher settling times.
Settling time is also a function of the CapSense clock. The higher the clock frequency, the smaller amount of settling time is needed.
In PSoC designer this can be adjusted by changing the settling time parameter of the user module.It is an 8bit value,and the possible values are 2 to 255.
The amount of delay introduced by this parameter(for the Cmod to reach Vstart)is given by,
Delay(us)=(6+21.(Settling time))/(CPU_SPEED MHz)