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Semaphore Value in Asynchronous Dual-Ports

Last Updated: June 27, 2011

- What are the uses of Semaphore latches?
- How are semaphore values read on the I/O bus?


Semaphore latches are used to “reserve” certain portions of memory

space to a particular port. If one port requires the use of a particular

address it writes a '0' to a semaphore latch which represents that address

space. Once written, that port will read the same latch to determine if

it gained access. If that port reads a '0' the attempt was successful and

that port now has access. A '1' represents a failed attempt. To effectively

utilize the semaphores, both ports must use the semaphores in a friendly

fashion. The dual port does not “enforce” the semaphores active state since

the part does not know which portion of memory is being allocated. Each

port must monitor the semaphores to make them effective.


Semaphores are implemented in hardware as a latch. There are eight

such latches, one for each semaphore that is available on the chip. The

semaphore that is being addressed is determined by the value of A0 - A2.

It is important to note that when accessing a semaphore, the SEM signal

must be held low, otherwise the operation will be interpreted as an access

of the memory array. Detailed information on semaphore implementation

is available in Cypress Asynchronous Dual-Ports Datasheets.


The value of the semaphore will only be driven out of the first byte of I/O

lines. In dual-ports with a bus width of x8 and x16, the native byte length

is 8 bits. In dual-ports with a bus width of x9, x18 or x36, the native byte

length is 9 bits.


For example, in dual-ports with a bus width of x36, I/O lines 0-8 will output

the semaphore value. I/O lines 9-35 will be in a high impedance (High-Z)

state. The table below shows other examples.


Bus Width

I/O Lines with Semaphore value

I/O Lines in High-Z state
















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